80286 Signal Descriptions MCQs : This section focuses on the "80286 Signal Descriptions". These Multiple Choice Questions (MCQs) should be practiced to improve the 80286 Signal Descriptions skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
If M/IO (active low) signal is ‘0’ then it indicates
A. I/O cycle
B. Memory cycle
C. I/O cycle or INTA cycle
D. I/O cycle or HALT cycle
Question 2
The 8 address lines, A23-A16 of 80286 are zero during
A. memory transfer
B. address transfer
C. memory to processor transfer
D. I/O transfer
Question 3
The 80286 is available in the package as
A. 68-pin PLCC (plastic leaded chip carrier)
B. 68-pin LCC (lead less chip carrier)
C. 68-pin PGA (pin grid array)
D. all of the mentioned
Question 4
The clock frequency applied at the CLK pin is internally divided by
A. 2
B. 4
C. 8
D. 1
Question 5
The LOCK (active low) is activated automatically by hardware using
A. XCHG signal
B. Interrupt acknowledge
C. Descriptor table access
D. All of the mentioned
Question 6
The minimum number of clock cycles required in an input pulse width of the RESET pin is
A. 4
B. 2
C. 8
D. 16
Question 7
The pin that is used to insert wait states in a bus cycle is
A. WAIT
B. BHE (active low)
C. READY (active low)
D. WAIT(active low)
Question 8
The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are
A. BUSY (active low)
B. PEACK (active low)
C. PEREQ
D. ERROR (active low)
Question 9
The signals S1 (active low), S2 (active low) are
A. output signals
B. indicate initiation of bus cycle
C. define type of bus cycle with M/IO (active low)
D. all of the mentioned
Question 10
To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
A. CAP and ground
B. Output pin and ground
C. CAP and Vcc
D. NMI and ground