8051 Interrupt Structure MCQ Questions & Answers

Question 1

All the interrupts at level 1 are polled in the second clock cycle of the

A. forth T state
B. fifth T state
C. third T state
D. none

Question 2

EA bit is used to

A. enable or disable external interrupts
B. enable or disable internal interrupts
C. enable or disable all the interrupts
D. none of the mentioned

Question 3

For an interrupt to be guaranteed served it should have duration of

A. one machine cycle
B. three machine cycles
C. two machine cycles
D. four machine cycles

Question 4

If two interrupts, of higher priority and lower priority occur simultaneously, then the service provided is for

A. interrupt of lower priority
B. interrupt of higher priority
C. lower & higher priority interrupts
D. none of the mentioned

Question 5

The bits that control the external interrupts are

A. ET0 and ET1
B. ET1 and ET2
C. EX0 and EX1
D. EX1 and EX2

Question 6

The external interrupts of 8051 can be enabled by

A. 4 LSBs of TCON register
B. Interrupt enable
C. priority register
D. all of the mentioned

Question 7

The minimum duration of the active low interrupt pulse for being sensed without being lost must be

A. greater than one machine cycle
B. equal to one machine cycle
C. greater than 2 machine cycles
D. equal to 2 machine cycles

Question 8

The number of priority levels that each interrupt of 8051 have is

A. 1
B. 2
C. 3
D. 4

Question 9

The priority level of an interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is

A. level 0
B. level 1
C. level 0 or level 1
D. none

Question 10

The service to an interrupt will be delayed if it appears during the execution of

A. RETI instruction
B. Instruction that writes to IE register
C. Instruction that writes to IP register
D. All of the mentioned