80586 (Pentium) Features MCQs : This section focuses on the "80586 (Pentium) Features". These Multiple Choice Questions (MCQs) should be practiced to improve the 80586 (Pentium) Features skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
A. super pipelined technique
B. multiple instruction issue
C. super pipelined technique and multiple instruction issue
D. none of the mentioned
Question 2
The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
A. super pipelined architecture
B. multiple instruction issue
C. very long instruction word architecture
D. superscalar architecture
Question 3
The branch target buffer is
A. four-way set-associative memory
B. has branch instruction address
C. has destination address
D. all of the mentioned
Question 4
The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
A. super pipelined architecture
B. multiple instruction issue
C. very long instruction word architecture
D. super scalar architecture
Question 5
The CPU has to wait until the execution stage to determine whether the condition is met in
A. unconditional branch
B. conditional branch
C. pipelined execution branch
D. none of the mentioned
Question 6
The memory device that holds branch target addresses for previously executed branches is
A. Tristate buffer
B. RAM
C. ROM
D. Branch target buffer
Question 7
The number of stages of the integer pipeline, U, of Pentium is
A. 2
B. 4
C. 3
D. 6
Question 8
The salient feature of Pentium is
A. superscalar architecture
B. superpipelined architecture
C. superscalar and superpipelined architecture
D. none of the mentioned
Question 9
Which of the following is a cache of Pentium?
A. data cache
B. data cache and instruction cache
C. instruction cache
D. none of the mentioned
Question 10
Which of the following is a class of architecture of MII (multiple instruction issue)?
A. super pipelined architecture
B. multiple instruction issue
C. very small instruction word architecture
D. super scalar architecture