8089 I/O Processor MCQs : This section focuses on the "8089 I/O Processor". These Multiple Choice Questions (MCQs) should be practiced to improve the 8089 I/O Processor skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
In the 8089 architecture, the address of memory table for channel-2 is calculated by
A. adding 16 to the contents of CCP
B. adding 8 to the contents of CCP
C. adding memory table address of channel-1
D. none of the mentioned
Question 2
The 8089 communicates with the host CPU using bus arbiter and controller in
A. tightly coupled configuration
B. loosely coupled configuration
C. tightly and loosely coupled configurations
D. none of the mentioned
Question 3
The 8089 shares the system bus and memory with the host CPU in
A. tightly coupled configuration
B. loosely coupled configuration
C. tightly and loosely coupled configurations
D. none of the mentioned
Question 4
The current channel status of program status word contains
A. source and destination address widths
B. bus load limit
C. interrupt control and servicing
D. all of the mentioned
Question 5
The IO device that can be interfaced with 8089 is
A. 16-bit IO
B. 8-bit IO
C. 64-bit IO
D. 16-bit and 8-bit IO
Question 6
The number of address lines used by the I/O processor in 8089 is
A. 20
B. 12
C. 16
D. 8
Question 7
The pin that is used for data transfer control and operation termination signals is
A. SINTR
B. EXT
C. DRQ and EXT
D. RQ (active low) or GT (active low)
Question 8
The pin that is used to inform the CPU that the previous operation is completed is
A. RQ (active low)
B. GT (active low)
C. DRQ
D. SINTR
Question 9
The registers that are used as source and destination pointers during DMA operations are
A. GB, GC
B. GC, BC
C. GC, GA
D. GA, GB
Question 10
Which of the following is not a general purpose register of 8089?
A. GA
B. BC
C. CX
D. MC