8237 DMA Interface MCQs : This section focuses on the "8237 DMA Interface". These Multiple Choice Questions (MCQs) should be practiced to improve the 8237 DMA Interface skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
Each bit in the request register is cleared by
A. under program control
B. generation of TC
C. generation of an external EOP
D. all of the mentioned
Question 2
In demand transfer mode of 8237, the device stops data transfer when
A. a TC (terminal count) is reached
B. an external EOP (active low) is detected
C. the DREQ signal goes inactive
D. all of the mentioned
Question 3
The block of 8237 that decodes the various commands given to the 8237 by the CPU is
A. timing and control block
B. program command control block
C. priority block
D. none of the mentioned
Question 4
The current address register is programmed by the CPU as
A. bit-wise
B. byte-wise
C. bit-wise and byte-wise
D. none of the mentioned
Question 5
The DMA request input pin that has the highest priority is
A. DREQ0
B. DREQ1
C. DREQ2
D. DREQ3
Question 6
The mode of 8237 in which the device transfers only one byte per request is
A. block transfer mode
B. single transfer mode
C. demand transfer mode
D. cascade mode
Question 7
The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is
A. CLEAR
B. SET
C. HLDA
D. RESET
Question 8
The priority between the DMA channels requesting the services can be resolved by
A. timing and control block
B. program command control block
C. priority block
D. none of the mentioned
Question 9
The register that can be automatically incremented or decremented, after each DMA transfer is
A. mask register
B. mode register
C. command register
D. current address register
Question 10
The register that holds the current memory address is
A. current word register
B. current address register
C. base address register
D. command register
Question 11
The register that holds the data during memory to memory data transfer is
A. mode register
B. temporary register
C. command register
D. mask register
Question 12
The register that keeps track of all the DMA channel pending requests and status of their terminal counts is
A. mask register
B. request register
C. status register
D. count register
Question 13
The register that maintains an original copy of the respective initial current address register and current word register is
A. mode register
B. base address register
C. command register
D. mask register
Question 14
The transfer of a block of data from one set of memory address to another takes place in
A. block transfer mode
B. demand transfer mode
C. memory to memory transfer mode
D. cascade mode
Question 15
To complete a DMA transfer, a memory to memory transfer requires
A. a read from memory cycle
B. a write to memory cycle
C. a read-from and write-to memory cycle
D. none of the mentioned
Question 16
When the count becomes zero in the current word register then
A. Input signal is enabled
B. Output signal is enabled
C. EOP (end of process) is generated
D. Start of process is generated
Question 17
Which of the following command is used to make all the internal registers of 8237 clear?
A. clear first/last flipflop
B. master clear command
C. clear mask register
D. none of the mentioned
Question 18
Which of these register’s contents is used for auto-initialization (internally)?
A. current word register
B. current address register
C. base address register
D. command register
Question 19
Which of the following is a type of DMA transfer?
A. memory read
B. memory write
C. verify transfer
D. all of the mentioned