# Combinational Logic Circuits MCQ Questions & Answers

Combinational Logic Circuits MCQs : This section focuses on the "Combinational Logic Circuits". These Multiple Choice Questions (MCQs) should be practiced to improve the Combinational Logic Circuits skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.

Question 1

How many inputs are required for a 1-of-10 BCD decoder?

A. 4
B. 8
C. 10
D. 1

Question 2

A magnitude comparator determines:

A. A B and if A B or A >> B
B. A B and if A > B or A < b
C. A = B and if A > B or A < b
D. A B and if A < b or a > B

Question 3

A multiplexed display:

A. accepts data inputs from one line and passes this data to multiple output lines
B. uses one display to present two or more pieces of information
C. accepts data inputs from multiple lines and passes this data to multiple output lines
D. accepts data inputs from several lines and multiplexes this input data to four BCD lines

Question 4

One application of a digital multiplexer is to facilitate:

A. code conversion
B. parity checking
C. parallel-to-serial data conversion
D. data generation

Question 5

A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n):

A. BCD matrix
B. display driver
C. encoder
D. decoder

Question 6

Which digital system translates coded characters into a more intelligible form?

A. encoder
B. display
C. counter
D. decoder

Question 7

Which type of decoder will select one of sixteen outputs, depending on the 4-bit binary input value?

B. dual octal outputs

Question 8

A basic multiplexer principle can be demonstrated through the use of a:

A. single-pole relay
B. DPDT switch
C. rotary switch
D. linear stepper

Question 9

Most demultiplexers facilitate which of the following?

B. single input, multiple outputs
C. ac to dc
D. odd parity to even parity

Question 10

Select one of the following statements that best describes the parity method of error detection:

A. Parity checking is best suited for detecting single-bit errors in transmitted codes.
B. Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
C. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
D. Parity checking is capable of detecting and correcting errors in transmitted codes.

Question 11

When two or more inputs are active simultaneously, the process is called:

A. first-in, first-out processing
B. priority encoding
C. ripple blanking
D. priority decoding

Question 12

In a BCD-to-seven-segment converter, why must a code converter be utilized?

A. No conversion is necessary.
B. to convert the 4-bit BCD into gray code
C. to convert the 4-bit BCD into 10-bit code
D. to convert the 4-bit BCD into 7-bit code

Question 13

A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?

A. 0
B. 3
C. 9
D. None. All outputs are HIGH.

Question 14

A decoder can be used as a demultiplexer by ________.

A. tying all enable pins LOW
B. tying all data-select lines LOW
C. tying all data-select lines HIGH
D. using the input lines for data selection and an enable line for data input

Question 15

A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

A. The output of the gate appears to be open.
B. The dim indication on the logic probe indicates that the supply voltage is probably low.
C. The dim indication is a result of a bad ground connection on the logic probe.
D. The gate may be a tristate device.

Question 16

An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?

A. Current tracer
B. Logic probe
C. Oscilloscope
D. Logic analyzer

Question 17

As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic nature. Of the possible faults listed, select the one that most probably is causing the problem.

A. A defective IC chip that is drawing excessive current from the power supply
B. A solar bridge between the inputs on the first IC chip on the board
C. An open input on the first IC chip on the board
D. A defective output IC chip that has an internal open to Vcc

Question 18

Convert BCD 0001 0010 0110 to binary.

A. 1111110
B. 1111101
C. 1111000
D. 1111111

Question 19

Convert BCD 0001 0111 to binary.

A. 10101
B. 10010
C. 10001
D. 11000

Question 20

Each "1" entry in a K-map square represents:

A. a HIGH for each input truth table condition that produces a HIGH output.
B. a HIGH output on the truth table for all LOW input combinations.
C. a LOW output for all possible HIGH input conditions.
D. a DON'T CARE condition for all possible input truth table combinations.

Question 21

How many 1-of-16 decoders are required for decoding a 7-bit binary number?

A. 5
B. 6
C. 7
D. 8

Question 22

How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?

A. 1
B. 2
C. 4
D. 8

Question 23

How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?

A. 1
B. 2
C. 3
D. 4

Question 24

How many data select lines are required for selecting eight inputs?

A. 1
B. 2
C. 3
D. 4

Question 25

How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?

A. 3
B. 4
C. 5
D. 6

Question 26

In HDL, LITERALS is/are:

A. digital systems.
B. scalars.
C. binary coded decimals.
D. a numbering system.

Question 27

In VHDL, macrofunctions is/are:

A. digital circuits.
B. analog circuits.
C. a set of bit vectors.
D. preprogrammed TTL devices.

Question 28

Looping on a K-map always results in the elimination of:

A. variables within the loop that appear only in their complemented form.
B. variables that remain unchanged within the loop.
C. variables within the loop that appear in both complemented and uncomplemented form.
D. variables within the loop that appear only in their uncomplemented form.

Question 29

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

A. A > B = 1, A < B = 0, A < B = 1
B. A > B = 0, A < B = 1, A = B = 0
C. A > B = 1, A < B = 0, A = B = 0
D. A > B = 0, A < B = 1, A = B = 1

Question 30

The carry propagation can be expressed as ________.

A. Cp = AB
B. Cp = A + B

Question 31

The design concept of using building blocks of circuits in a PLD program is called a(n):

A. hierarchical design.
B. architectural design.
C. digital design.
D. verilog.

Question 32

The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.)

A. AND/OR
B. NAND
C. NOR
D. OR/AND

Question 33

Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1. What are the values for the sum and carry output?

A. 4321 = 0111, Cout = 0
B. 4321 = 1111, Cout = 1
C. 4321 = 1011, Cout = 1
D. 4321 = 1100, Cout = 1

Question 34

What is the indication of a short on the input of a load gate?

A. Only the output of the defective gate is affected.
B. There is a signal loss to all gates on the node.
C. The affected node will be stuck in the LOW state.
D. There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.

Question 35

What is the indication of a short to ground in the output of a driving gate?

A. Only the output of the defective gate is affected.
B. There is a signal loss to all load gates.
C. The node may be stuck in either the HIGH or the LOW state.
D. The affected node will be stuck in the HIGH state.

Question 36

What will a design engineer do after he/she is satisfied that the design will work?

A. Put it in a flow chart
B. Program a chip and test it
C. Give the design to a technician to verify the design
D. Perform a vector test

Question 37

When adding an even parity bit to the code 110010, the result is ________.

A. 1110010
B. 1111001
C. 110010
D. 1101

Question 38

Which gate is best used as a basic comparator?

A. NOR
B. OR
C. Exclusive-OR
D. AND

Question 39

Which of the following combinations cannot be combined into K-map groups?

A. Corners in the same row
B. Corners in the same column
C. Diagonal corners
D. Overlapping combinations

Question 40

Which of the following combinations of logic gates can decode binary 1101?

A. One 4-input AND gate
B. One 4-input AND gate, one OR gate
C. One 4-input NAND gate, one inverter
D. One 4-input AND gate, one inverter

Question 41

Which of the following expressions is in the product-of-sums form?

A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD

Question 42

Which of the following expressions is in the sum-of-products form?

A. (A + B)(C + D)
B. (AB)(CD)
C. AB(CD)
D. AB + CD

Question 43

Which of the following is an important feature of the sum-of-products form of expressions?

A. All logic circuits are reduced to nothing more than simple AND and OR operations.
B. The delay times are greatly reduced over other forms.
C. No signal must pass through more than two gates, not including inverters.
D. The maximum number of gates that any signal must pass through is reduced by a factor of two.

Question 44

Which of the following statements accurately represents the two BEST methods of logic circuit simplification?

A. Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis
C. Actual circuit trial and error evaluation and waveform analysis
D. Boolean algebra and actual circuit trial and error evaluation