Counters MCQs : This section focuses on the "Counters". These Multiple Choice Questions (MCQs) should be practiced to improve the Counters skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
A. When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
B. When MR1 and MR2 are both HIGH, all Qs will be reset to one.
C. MR1 and MR2 are provided to synchronously reset all four flip-flops.
D. To enable the count mode, MR1 and MR2 must be held LOW.
The terminal count of a modulus-11 binary counter is ________.
After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?
Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.
Which of the following statements are true?
A. Asynchronous events do not occur at the same time.
B. Asynchronous events are controlled by a clock.
C. Synchronous events do not need a clock to control them.
D. Only asynchronous events need a control clock.
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns
Once an up-/down-counter begins its count sequence, it cannot be reversed.
How many natural states will there be in a 4-bit ripple counter?
How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
A. 128 gates, 6 inputs to each gate
B. 64 gates, 5 inputs to each gate
C. 64 gates, 6 inputs to each gate
D. 128 gates, 5 inputs to each gate
A counter circuit is usually constructed of ____________
A. A number of latches connected in cascade form
B. A number of NAND gates connected in cascade form
C. A number of flip-flops connected in cascade
D. A number of NOR gates connected in cascade form
The hexadecimal equivalent of 15,536 is ________.
How can a digital one-shot be implemented using HDL?
A. By using a resistor and a capacitor
B. By applying the concept of a counter
C. By using a library function
D. By applying a level trigger
Why can a synchronous counter operate at a higher frequency than a ripple counter?
A. The flip-flops change one after the other.
B. The flip-flops change at the same time.
C. A synchronous counter cannot operate at higher frequencies.
D. A ripple counter is faster.
How many different states does a 2-bit asynchronous counter have?
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
A. input clock pulses are applied only to the first and last stages.
B. input clock pulses are applied only to the last stage.
C. input clock pulses are applied simultaneously to each stage.
D. input clock pulses are not used to activate any of the counter stages.
In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
A. A trigger edge has occurred and we must load the counter.
B. The counter is zero and we need to keep it at zero.
C. The shift register is reset.
D. The counter is not zero and we need to count down by one.
A decimal counter has ______ states.
An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
MOD-6 and MOD-12 counters and multiples are most commonly used as:
A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters
What is the difference between a 7490 and a 7493?
A. 7490 is a MOD-10, 7493 is a MOD-16
B. 7490 is a MOD-16, 7493 is a MOD-10
C. 7490 is a MOD-12, 7493 is a MOD-16
D. 7490 is a MOD-10, 7493 is a MOD-12
Three decade counter would have ____________
A. 2 BCD counters
B. 3 BCD counters
C. 4 BCD counters
D. 5 BCD counters
A modulus-10 counter must have ________.
A. 10 flip-flops
C. 2 flip-flops
D. synchronous clocking
A seven-segment, common-anode LED display is designed for:
A. all cathodes to be wired together
B. one common LED
C. a HIGH to turn off each segment
D. disorientation of segment modules
A multiplexed display being driven by a logic circuit:
A. accepts data inputs from one line and passes this data to multiple output lines
B. accepts data inputs from several lines and allows one of them at a time to pass to the output
C. accepts data inputs from multiple lines and passes this data to multiple output lines
D. accepts data inputs from several lines and multiplexes this input data to four BCD lines
To operate correctly, starting a ring counter requires:
A. clearing one flip-flop and presetting all the others.
B. clearing all the flip-flops.
C. presetting one flip-flop and clearing all the others.
D. presetting all the flip-flops.
How many different states does a 3-bit asynchronous counter have?
Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?
A. Five flip-flops, three AND gates
B. Seven flip-flops, five AND gates
C. Four flip-flops, ten AND gates
D. Six flip-flops, four AND gates
List which pins need to be connected together on a 7493 to make a MOD-12 counter.
A. 12 to 1, 11 to 3, 9 to 2
B. 12 to 1, 11 to 3, 12 to 2
C. 12 to 1, 11 to 3, 8 to 2
D. 12 to 1, 11 to 3, 1 to 2
Which is not an example of a truncated modulus?
Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
A. external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
B. modifying BCD counters to change states on every second input clock pulse
C. modifying asynchronous counters to change states on every second input clock pulse
D. elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts
The terminal count of a 3-bit binary counter in the DOWN mode is ________.
What is the difference between combinational logic and sequential logic?
A. Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.
B. Combinational and sequential circuits are both triggered by timing pulses.
C. Neither circuit is triggered by timing pulses.
Which of the following is an invalid state in an 8421 BCD counter?
A 4-bit counter has a maximum modulus of ________.
List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.
A. RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
C. RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
D. RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
In digital logic, a counter is a device which ____________
A. Counts the number of outputs
B. Stores the number of times a particular event or process has occurred
C. Stores the number of times a clock pulse rises and falls
D. Counts the number of inputs
For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
A. Cp, the same clock input line
B. CE, the same clock input line
C. , the terminal count output
D. , both clock input lines
Which of the following is an invalid output state for an 8421 BCD counter?
Which of the following statements best describes the operation of a synchronous up-/down-counter?
A. The counter can count in either direction, but must continue in that direction once started.
B. The counter can be reversed, but must be reset before counting in the other direction.
C. In general, the counter can be reversed at any point in its counting sequence.
D. The count sequence cannot be reversed, once it has begun, without first resetting the counter to zero.
How many flip-flops are required to construct a decade counter?
List which pins need to be connected together on a 7492 to make a MOD-12 counter.
A. 1 to 12, 11 to 6, 9 to 7
B. 1 to 12, 12 to 6, 11 to 7
C. 1 to 12, 9 to 6, 8 to 7
D. 1 to 12
A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.
A. 10 kHz
B. 20 kHz
C. 30 kHz
D. 60 kHz
Three cascaded decade counters will divide the input frequency by ________.
A BCD counter is a ________.
A. binary counter
B. full-modulus counter
C. decade counter
D. divide-by-10 counter
The parallel outputs of a counter circuit represent the _____________
A. Parallel data word
B. Clock frequency
C. Counter modulus
D. Clock count
What is the difference between a 7490 and a 7492?
A. 7490 is a MOD-12, 7492 is a MOD-10
B. 7490 is a MOD-12, 7492 is a MOD-16
C. 7490 is a MOD-16, 7492 is a MOD-10
D. 7490 is a MOD-10, 7492 is a MOD-12
In an HDL ring counter, many invalid states are included in the programming by:
A. using a case statement.
B. using an elsif statement.
C. including them under others.
D. the ser_in line.
One of the major drawbacks to the use of asynchronous counters is:
A. low-frequency applications are limited because of internal propagation delays
B. high-frequency applications are limited because of internal propagation delays
C. asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
D. asynchronous counters do not have propagation delays and this limits their use in high-frequency applications
BCD counter is also known as ____________
A. Parallel counter
B. Decade counter
C. Synchronous counter
D. VLSI counter
What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
A. 15 ns
B. 22 ns
C. 60 ns
D. 88 ns
Integrated-circuit counter chips are used in numerous applications including:
A. timing operations, counting operations, sequencing, and frequency multiplication
B. timing operations, counting operations, sequencing, and frequency division
C. timing operations, decoding operations, sequencing, and frequency multiplication
D. data generation, counting operations, sequencing, and frequency multiplication
How many types of the counter are there?
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
A. 0 to 2n
B. 0 to 2n + 1
C. 0 to 2n – 1
D. 0 to 2n+1/2
For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?
A. By using a counter
B. By using an active clock
C. By using an immediate reload
D. By using edge trapping
Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?
A. b, c, d, e, f, and g
B. a, c, d, e, f, and g
C. a, b, c, d, and f
D. b, c, d, e, and f
Ripple counters are also called ____________
A. SSI counters
B. Asynchronous counters
C. Synchronous counters
D. VLSI counters
The terminal count of a typical modulus-10 binary counter is ________.
A counter with a modulus of 16 acts as a ________.
A. divide-by-8 counter
B. divide-by-16 counter
C. divide-by-32 counter
D. divide-by-64 counter
How many flip-flops are required to make a MOD-32 binary counter?
Synchronous construction reduces the delay time of a counter to the delay of:
A. all flip-flops and gates
B. all flip-flops and gates after a 3 count
C. a single gate
D. a single flip-flop and a gate
Which of the following is an example of a counter with a truncated modulus?
Which of the following is a type of shift register counter?
A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.
A. 12 ms
B. 24 ns
C. 48 ns
D. 60 ns
Three cascaded modulus-5 counters have an overall modulus of ________.
Four cascaded modulus-10 counters have an overall modulus of ________.
Which segments of a seven-segment display would be required to be active to display the decimal digit 2?
A. a, b, d, e, and g
B. a, b, c, d, and g
C. a, c, d, f, and g
D. a, b, c, d, e, and f
A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?
A. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
B. Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
C. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
D. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz
When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.
A principle regarding most display decoders is that when the correct input is present, the related output will switch:
B. to high impedance
C. to an open
The final output of a modulus-8 counter occurs one time for every ________.
A. 8 clock pulses
B. 16 clock pulses
C. 24 clock pulses
D. 32 clock pulses
Which of the following procedures could be used to check the parallel loading feature of a counter?
A. Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.
B. Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.
C. Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.
D. Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.
A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.
A. 500 kHz
B. 1,500 kHz
C. 6 MHz
D. 5 MHz
Synchronous counter is a type of ____________
A. SSI counters
B. LSI counters
C. MSI counters
D. VLSI counters
The parallel outputs of a counter circuit represent the:
A. parallel data word
B. clock frequency
C. counter modulus
D. clock count
What is meant by parallel load of a counter?
A. Each FF is loaded with data on a separate clock.
B. The counter is cleared.
C. All FFs are preset with data.