Question 1
By how many modeling styles, the gates in VHDL can be implemented?
A. 1
B. 2
C. 3
D. 4
View Answer
Answer: Option C
Explanation:
There are three modeling styles in VHDL in which we may implement any kind of logic or logic gate. These modeling styles are behavioral modeling, dataflow modeling and structural modeling.
Question 2
For gates, which of the following modeling style will corresponds to shortest code?
A. Behavioral
B. Data flow
C. Structural
D. Both data flow and behavioral
View Answer
Answer: Option B
Explanation:
Since in case of dataflow modeling we just need to define the relation between inputs and outputs using some logical function. So, gates can be modeled be using dataflow style in just one line. Whereas Behavioral needs selected assignment and structural used component declaration and instantiation.
Question 3
Generally, structural modeling is used with another modeling style.
A. TRUE
B. FALSE
View Answer
Answer: Option A
Explanation:
We can’t describe a logic gate or circuit by using a structural model alone. At least one more architecture is needed to properly describe the behavior of the circuit. So generally more than one architectures are used.
Question 4
In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
A. Incorrect interconnections
B. Concurrent execution of statements
C. Mismatch of ports name and switches
D. Wrong libraries included
View Answer
Answer: Option B
Explanation:
A CPLD is a device which has many input outputs and logic gates and it also includes interconnection between them. The inputs are arranged in the form of switch banks, the gate may perform different due to concurrency of the statement. Due to concurrent statements, the state of a switch can vary and which can affect the output.
Question 5
Sometimes gates modeled with ________ modeling may behave differently.
A. Dataflow
B. Behavioral
C. Structural
D. Structural and Behavioral
View Answer
Answer: Option A
Explanation:
Sometimes, dataflow modeling doesn’t behave as we want it to. This different behavior can be with any of the gate. For example, OR gate may behave as AND gate for instance. This occurs at the time of synthesis due to switches in the switch bank.
Question 6
The odd behavior of gates in dataflow modeling may be the result of ________
A. Sequential statements
B. Wrong logic definitions
C. Concurrency
D. Inappropriate assignments
View Answer
Answer: Option C
Explanation:
The VHDL code is concurrent code and it has its own advantages and disadvantages. Concurrency of VHDL results in faster execution. In some PAL or PLA device, it may be like executing AND after OR execution which may result in different results.
Question 7
What is the minimum number of NAND gates required to implement an EXOR gate?
A. 2
B. 3
C. 4
D. 5
View Answer
Answer: Option C
Explanation:
We can implement an EXOR gate with a minimum of 4 NAND gates. However, when we follow the conventional way to convert an EXOR logic into the NADN logic, then the number of logic gates required is 5, but 1 of them is redundant and therefore, we can implement EXOR get by using 4 NAND gates.
Question 8
Which of the following gate is a universal gate?
A. AND
B. NAND
C. EXOR
D. EXNOR
View Answer
Answer: Option B
Explanation:
NAND and NOR are two universal gates. They are called so because we may implement any kind of basic logic gate by using any of these two universal logic gates. By using NAND or NOR, we may implement AND, OR, NOT and EXOR gates.
Question 9
Which of the following is a basic building block of digital logic?
A. Wires
B. Nets
C. Gates
D. Flip-flops
View Answer
Answer: Option C
Explanation:
Any kind of digital logic can be synthesized by basic logic gates like or gate, and gate, not gate, etc. By using these simple gates, we may synthesize many difficult circuits or functions. So, gates are the building block for any digital logic.
Question 10
Which of the following is not needed when modeling a simple gate?
A. Library
B. Entity
C. Architecture
D. Configuration
View Answer
Answer: Option D
Explanation:
Modeling a gate is a really easy task. There is no need for adding some CONFIGURATIONS to the design. The gates can be designed with any modeling style without using any kind of configuration statement. Also, describing architecture is essential along with entity. Package is needed to have some basic functions.