Digital Design MCQs : This section focuses on the "Digital Design". These Multiple Choice Questions (MCQs) should be practiced to improve the Digital Design skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
A Schmitt trigger has VT+ = 2.0 V and VT– = 1.2 V. What is the hysteresis voltage of the Schmitt trigger?
A. 0.4 volt
B. 0.6 volt
C. 0.8 volt
D. 1.2 volts
A Schmitt trigger:
A. has two trip points
B. is a zero crossing detector
C. has positive feedback
D. has two trip points and positive feedback
A settable flip-flop's normal starting state when power is first applied to a circuit is always the ________ state.
An optocoupler is an integrated circuit with an LED and a zener diode encased in the same package.
Can the automatic RC circuit be used to set a flip-flop rather than reset the flip-flop?
Decoupling capacitors should be tied from VCC on one device to ground on a different device.
Define a race condition for a flip-flop.
A. The inputs to a trigger device are changing slightly before the active trigger edge.
B. The inputs to a trigger device are changing slightly after the active trigger edge.
C. The inputs to a trigger device are changing at the same time as the active trigger edge.
How much setup time (ts) is required for the 74LS76?
A. 5 ns
B. 10 ns
C. 20 ns
D. 40 ns
In the automatic reset circuit for a flip-flop, how long does it take the capacitor to completely charge?
A. 1 time constant (RC)
B. 2 time constants (RC)
C. 5 time constants (RC)
D. 10 time constants (RC)
Is the propagation delay from the clock to the output for the 7476 the same as the delay from the set or reset to the output?
Look up the propagation delay from the clock to the output for the 7476. Are the HIGH-to-LOW and LOW-to-HIGH propagation delays the same?
B. no, tPLH = 25 ns, tPHL = 40 ns
C. no, tPLH = 40 ns, tPHL = 25 ns
D. no, tPHL = 25 ns, tPLH = 40 ns
One example for the use of a Schmitt trigger is as a(n):
A. switch debouncer
C. astable oscillator
D. transition pulse generator
Setup time specifies:
A. the minimum time the control levels need to be maintained on the inputs prior to the triggering edge of the clock in order to be reliably clocked into the flip-flop
B. the maximum time interval required for the control levels to remain on the inputs before the triggered edge of the clock in order for the data to be reliably clocked out of the flip-flop
C. how long the operator has to get the flip-flop running before the maximum power level is exceeded
D. how long it takes the output to change states after the clock has transitioned
The ________ circuit overcomes the problem of switching caused by jitter on the inputs.
A. astable multivibrator
B. monostable multivibrator
C. bistable multivibrator
D. Schmitt trigger
The main concern when using a pull-down resistor is:
A. the low power dissipation of the resistor
B. it will keep a floating terminal LOW
C. the high power dissipation of the resistor
D. it will cause false triggering
The purpose of a pull-up resistor is to keep a terminal at a ________ level when it would normally be at a ________ level.
A. LOW, float
B. HIGH, float
C. clock, float
D. pulsed, float
What is the difference between setup time and hold time?
A. Setup time occurs after the active clock edge, hold time occurs before the active clock edge.
B. Setup time occurs before the active clock edge, hold time occurs after the active clock edge.
C. Setup time and hold time both occur at the active clock edge.
What is the major advantage of the J-K flip-flop over the S-R flip-flop?
A. The J-K flip-flop is much faster.
B. The J-K flip-flop does not have propagation delay problems.
C. The J-K flip-flop has a toggle state.
D. The J-K flip-flop has two outputs.
What would be the output voltage of a 7814 voltage regulator?
A. –14 V dc
B. +14 V dc
C. –8 V dc
D. +8 V dc
When the inputs to a flip-flop are changing at the same time that the active trigger edge of the input clock is making its transition, this condition is called:
C. slave loading
D. pulse timing
Which of the following circuit parameters would be most likely to limit the maximum operating frequency of a flip-flop?
A. setup and hold time
B. clock pulse HIGH and LOW time
C. propagation delay time
D. clock transition time
Which of the following flip-flop timing parameters indicates the time it takes a Q output to respond to a Cp input?
A. ts, th
B. tPHL, tPLH
C. tw (L), tw (H)
Why does the data sheet for the 7476 only give a minimum value for the clock pulse width (both HIGH and LOW)?
A. nominal value
B. best-case condition
C. worst-case condition
Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?
A. to provide a triangle wave
B. to provide a sine wave
C. to provide a rounded pulse waveform
D. to provide a sharp pulse waveform
Why should a LED be pulled LOW from a logic gate rather than pulled HIGH?
A. LOW-level current is smaller.
B. LOW-level current is larger.
C. HIGH-level current is larger.
D. LOW-level current is smaller and HIGH-level current is larger.
Why would a delay gate be needed for a digital circuit?
A. A delay gate is never needed.
B. to provide for setup times
C. to provide for hold times
D. to provide for setup times and hold times