Digital Electronics MCQs : This section focuses on the "Digital Electronics". These Multiple Choice Questions (MCQs) should be practiced to improve the Digital Electronics skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
1's complement of 11100110 is
A. 11001
B. 10000001
C. 11010
D. 0
Question 2
2's complement of binary number 0101 is
A. 1011
B. 1111
C. 1101
D. 1110
Question 3
7BF16 = __________ 2
A. 0111 1011 1110
B. 0111 1011 1111
C. 0111 1011 0111
D. 0111 1011 0011
Question 4
A 12 bit ADC is used to convert analog voltage of 0 to 10 V into digital. The resolution is
A. 2.44 mV
B. 24.4 mV
C. 1.2 V
D. none of the above
Question 5
A carry look ahead adder is frequently used for addition because
A. it costs less
B. it is faster
C. it is more accurate
D. is uses fewer gates
Question 6
A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time
A. 8 μ sec
B. 10 μ sec
C. 2 μ sec
D. 5 μ sec
Question 7
A decade counter skips
A. binary states 1000 to 1111
B. binary states 0000 to 0011
C. binary states 1010 to 1111
D. binary states 1111 to higher
Question 8
A device which converts BCD to seven segment is called
A. encoder
B. decoder
C. multiplexer
D. none of these
Question 9
A full adder can be made out of
A. two half adders
B. two half adders and a OR gate
C. two half adders and a NOT gate
D. three half adders
Question 10
A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these flip flops and operating at 10 MHz is
A. 16
B. 64
C. 128
D. 256
Question 11
A memory system of size 16 k bytes is to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is
A. 2
B. 4
C. 8
D. 18
Question 12
A ring counter with 5 flip flops will have
A. 5 states
B. 10 states
C. 32 states
D. infinite states
Question 13
A three state switch has three outputs. These are
A. low, low and high
B. low, high, high
C. low. floating, low
D. low, high, floating
Question 14
AB + AB =
A. B
B. A
C. 1
D. 0
Question 15
An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is 10000000 the range of outputs is
A. 994 to 1014 μA
B. 990 to 1020 μA
C. 800 to 1200 μA
D. none of the above
Question 16
An AND gate has two inputs A and B and one inhibit input 3, Output is 1 if
A. A = 1, B = 1, S = 1
B. A = 1, B = 1, S = 0
C. A = 1, B = 0, S = 1
D. A = 1, B = 0, S = 0
Question 17
An OR gate has 4 inputs. One input is high and the other three are low. The output
A. is low
B. is high
C. is alternately high and low
D. may be high or low depending on relative magnitude of inputs
Question 18
BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver. The segments which will lit up are
A. a, b, d
B. a, b, c
C. all
D. a, b, g, c, d
Question 19
Both OR and AND gates can have only two inputs.
A. TRUE
B. FALSE
Question 20
Decimal 43 in hexadecimal and BCD number system is respectively.
A. B2, 01000011
B. 2B, 01000011
C. 2B, 00110100
D. B2, 01000100
Question 21
Decimal number 10 is equal to binary number
A. 1110
B. 1010
C. 1001
D. 1000
Question 22
For the minterm designation Y = ∑ m (1, 3, 5, 7) the complete expression is
A. Y = A BC + A B C
B. Y = A B C + A B C + ABC + A BC
C. Y = A B C + A B C + ABC + A BC
D. Y = A B C + ABC + A BC + A BC
Question 23
In 2's complement representation the number 11100101 represents the decimal number
A. 37
B. -31
C. 27
D. -27
Question 24
In a 7 segment display, LEDs b and c lit up. The decimal number displayed is
A. 9
B. 7
C. 3
D. 1
Question 25
In a BCD to 7 segment decoder the minimum and maximum number of outputs active at any time is
A. 2 and 7
B. 3 and 7
C. 1 and 6
D. 3 and 6
Question 26
In a ripple counter,
A. whenever a flip flop sets to 1, the next higher FF toggles
B. whenever a flip flop sets to 0, the next higher FF remains unchanged
C. whenever a flip flop sets to 1, the next higher FF faces race condition
D. whenever a flip flop sets to 0, the next higher FF faces race condition
Question 27
In register index addressing mode the effective address is given by
A. index register value
B. sum of the index register value and the operand
C. operand
D. difference of the index register value and the operand
Question 28
In the expression A + BC, the total number of minterms will be
A. 2
B. 3
C. 4
D. 5
Question 29
Maxterm designation for A + B + C is
A. M0
B. M1
C. M3
D. M4
Question 30
Minimum number of 2-input NAND gates required to implement the function F = (x + y) (Z + W) is
A. 3
B. 4
C. 5
D. 6
Question 31
The access time of a word in 4 MB main memory is 100 ms. The access time of a word in a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95. The efficiency of memory access time is
A. 9.5 ns
B. 14.5 ns
C. 20 ns
D. 95 ns
Question 32
The basic storage element in a digital system is
A. flip flop
B. counter
C. multiplexer
D. encoder
Question 33
The expression Y = pM (0, 1, 3, 4) is
A. POS
B. SOP
C. Hybrid
D. none of the above
Question 34
The fixed count that should be used so that the output register will represent the input for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).
A. 110
B. 10
C. 1111
D. 11101
Question 35
The greatest negative number which can be stored is 8 bit computer using 2's complement arithmetic is
A. -256
B. -128
C. -255
D. -127
Question 36
The hexadecimal number (3E8)16 is equal to decimal number
A. 1000
B. 982
C. 768
D. 323
Question 37
The number of digits in octal system is
A. 8
B. 7
C. 9
D. 10
Question 38
The number of distinct Boolean expression of 4 variables is
A. 16
B. 256
C. 1024
D. 65536
Question 39
The output of a half adder is
A. SUM
B. CARRY
C. SUM and CARRY
D. none of the above
Question 40
The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is
A. 8
B. 9
C. 10
D. 11
Question 41
Which device has one input and many outputs?
A. Multiplexer
B. Demultiplexer
C. Counter
D. Flip flop
Question 42
Which of the following is non-saturating?
A. TTL
B. CMOS
C. ECL
D. Both (a) and (b)
Question 43
Zero suppression is not used in actual practice.
A. TRUE
B. FALSE
Question 44
How many basic logic gates are there?
A. 1
B. 2
C. 3
D. 4
Question 45
In Boolean algebra, what will not (A + not (B)).C) be equal to?
A. 1
B. 2
C. 3
D. 4
Question 46
The truth table shows both the input and output signals.
A. True
B. False
Question 47
What should be done to obtain an OR gate from a NAND gate?
A. We need only 3 NAND gates
B. We need two NOT gates obtained from NAND gates and one NAND gate
C. We need 3 NOT gates obtained from NAND gates and 3 NAND gates
D. We need 2 NAND gates and 4 AND gates obtained from NAND gates.
Question 48
Which gate will a NAND gate be equivalent to when two inputs of NAND gates are shorted?
A. AND gate
B. OR gate
C. NAND gate
D. NOT gate
Question 49
Which of the following gates can have only one input?
A. OR gate
B. NOT gate
C. AND gate
D. NAND gate
Question 50
Which of the following is correct about logic gates?
A. Logic gates have one or more input signals and only one output signal
B. Logic gates have only one input and output signal
C. Logic gates are analogous circuits
D. Logic gates have only one input and many output signals
Question 51
Identify the type of gate below from the equation
A. ex-nor gate
B. or gate
C. ex-or gate
D. nand gate
Question 52
Parity systems are defined as either________ or ________ and will add an extra ________ tothe digital information being transmitted.
A. positive, negative, byte
B. odd, even, bit
C. upper, lower, digit
D. on, off, decimal
Question 53
A binary-weighted-input digital-to-analog converter has a feedback resistor, Rf, of 12 k. If 50 A of current is through the resistor, voltage out of the circuit is ________.
A. 0.6 v
B. –0.6 v
C. 0.1 v
D. –0.1 v
Question 54
The prime implicant which has at least one element that is not present in any other implicant is known as
A. essential prime implicant
B. implicant
C. complement
D. prime complement
Question 55
Product-of-Sums expressions can be implemented using
A. 2-level or-and logic circuits
B. 2-level nor logic circuits
C. 2-level xor logic circuits
D. both 2-level or-and and nor logic circuits
Question 56
Each product term of a group, w’.x.y’ and w.y, represents the in that group.
A. input
B. pos
C. sum-of-minterms
D. sum of maxterms
Question 57
It should be kept in mind that don’t care terms should be used along with the terms that are present in
A. minterms
B. expressions
C. k-map
D. latches
Question 58
In case of XOR/XNOR simplification we have to look for the following
A. diagonal adjacencies
B. offset adjacencies
C. straight adjacencies
D. both diagonal and offset adjencies
Question 59
The time required for a gate or inverter to change its state is called
A. rise time
B. decay time
C. propagation time
D. charging time
Question 60
Odd parity of word can be conveniently tested by
A. or gate
B. and gate
C. nand gate
D. xor gate
Question 61
The number of full and half adders are required to add 16-bit number is
A. 8 half adders, 8 full adders
B. 1 half adders, 15 full adders
C. 16 half adders, 0 full adders
D. 4 half adders, 12 full adders
Question 62
An OR gate can be imagined as
A. switches connected in series
B. switches connected in parallel
C. mos transistor connected in series
D. bjt transistor connected in series
Question 63
If a DAC has a full-scale, or maximum, output of 12 V and accuracy of 0.1%, then the maximum error for any output voltage is ________.
A. 12 v
B. 120 mv
C. 12 mv
D. 0 v
Question 64
In parts of the processor, adders are used to calculate
A. addresses
B. table indices
C. increment and decrement operators
D. all of the mentioned
Question 65
If A and B are the inputs of a half adder, the sum is given by
A. a and b
B. a or b
C. a xor b
D. a ex-nor b
Question 66
If A and B are the inputs of a half adder, the carry is given by
A. a and b
B. a or b
C. a xor b
D. a ex-nor b
Question 67
Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a) and displays the waveforms shown in figure (b). The actual analyzer display shows all four data outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output lines show a LOW level output. What is wrong, if anything, with the circuit?
A. nothing is wrong, according to the display. the outputs are in the open state and should show zero output voltage.
B. the circuit is in the read mode and the outputs, q0-q3, should reflect the contents of the memory at that address. the chip is defective; replace the chip.
C. the circuit is in the mode and should be writing the contents of the selected address to q0–q3.
D. the q0–q3 lines can be either low or high, since the chip is in the tristate mode in which case their level is unpredictable.
Question 68
Half-adders have a major limitation in that they cannot
A. accept a carry bit from a present stage
B. accept a carry bit from a next stage
C. accept a carry bit from a previous stage
D. accept a carry bit from the following stages
Question 69
The difference between half adder and full adder is
A. half adder has two inputs while full adder has four inputs
B. half adder has one output while full adder has two outputs
C. half adder has two inputs while full adder has three inputs
D. all of the mentioned
Question 70
What is the meaning of RAM, and what is its primary role?
A. readily available memory; it is the first level of memory used by the computer in all of its operations.
B. random access memory; it is memory that can be reached by any sub- system within a computer, and at any time.
C. random access memory; it is the memory used for short-term temporary data storage within the computer.
D. resettable automatic memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to.
Question 71
If A, B and C are the inputs of a full adder then the sum is given by
A. a and b and c
B. a or b and c
C. a xor b xor c
D. a or b or c
Question 72
If A, B and C are the inputs of a full adder then the carry is given by
A. a and b or (a or b) and c
B. a or b or (a and b) c
C. (a and b) or (a and b)c
D. a xor b xor (a xor b) and c
Question 73
How many AND, OR and EXOR gates are required for the configuration of full
A. 1, 2, 2002
B. 2, 1, 2002
C. 3, 1, 2002
D. 4, 0, 1
Question 74
Half subtractor is used to perform subtraction of
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Question 75
Let A and B is the input of a subtractor then the output will be
A. a xor b
B. a and b
C. a or b
D. a exnor b
Question 76
Let A and B is the input of a subtractor then the borrow will be
A. a and b’
B. a’ and b
C. a or b
D. a and b
Question 77
Full subtractor is used to perform subtraction of
A. 2 bits
B. 3 bits
C. 4 bits
D. 8 bits
Question 78
Convert the following decimal number to 8-bit binary.
A. 101110112
B. 110111012
C. 101111012
D. 101111002
Question 79
The output of a full subtractor is same as
A. half adder
B. full adder
C. half subtractor
D. decoder
Question 80
The full subtractor can be implemented using
A. two xor and an or gates
B. two half subtractors and an or gate
C. two multiplexers and an and gate
D. two comparators and an and gate
Question 81
Controlled buffers can be useful
A. to control the circuit’s output into the bus
B. in comparison of component’s output with its input
C. in increasing the output from its low input
D. all of the mentioned
Question 82
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
A. ex-nor gate
B. or gate
C. ex-or gate
D. nand gate
Question 83
What is the major difference between half- adders and full-adders?
A. full-adders are made up of two half-adders
B. full adders can handle double-digit numbers
C. full adders have a carry input capability
D. half adders can handle only single-digit numbers
Question 84
When performing subtraction by addition in the 2’s-complement system
A. the minuend and the subtrahend are both changed to the 2’s-complement
B. the minuend is changed to 2’s- complement and the subtrahend is left in its original form
C. the minuend is left in its original form and the subtrahend is changed to its 2’s- complement
D. the minuend and subtrahend are both left in their original form
Question 85
The selector inputs to an arithmetic/logic unit (ALU) determine the
A. selection of the ic
B. arithmetic or logic function
C. data word selection
D. clock frequency to be used
Question 86
The given hexadecimal number (1E.53)16 is equivalent to
A. (35.684)8
B. (36.246)8
C. (34.340)8
D. (35.599)8
Question 87
The octal number (651.124)8 is equivalent to
A. 16
B. (1b0.10)16
C. (1a8.a3)16
D. (1b0.b0)16
Question 88
The octal equivalent of the decimal number (417)10 is
A. (641)8
B. (619)8
C. (640)8
D. (598)8
Question 89
Convert the hexadecimal number (1E2)16 to decimal:
A. 480
B. 483
C. 482
D. 484
Question 90
(170)10 is equivalent to
A. (fd)16
B. (df)16
C. (aa)16
D. (af)16
Question 91
Convert the binary number (01011.1011)2 into decimal:
A. (11.6875)10
B. (11.5874)10
C. (10.9876)10
D. (10.7893)10
Question 92
On addition of +38 and -20 using 2’s complement, we get
A. 11110001
B. 100001110
C. 10010
D. 110101011
Question 93
If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be
A. 0
B. 1
C. floating
D. high impedance
Question 94
On addition of -46 and +28 using 2’s complement, we get
A. 101110
B. 101110
C. 101111
D. 1001111
Question 95
The decimal number system represents the decimal number in the form of
A. hexadecimal
B. binary coded
C. octal
D. decimal
Question 96
On subtracting +28 from +29 using 2’s complement, we get
A. 11111010
B. 111111001
C. 100001
D. 1
Question 97
29 input circuit will have total of
A. 32 entries
B. 128 entries
C. 256 entries
D. 512 entries
Question 98
The decimal number 10 is represented in its BCD form as
A. 10100000
B. 1010111
C. 10000
D. 101011
Question 99
BCD adder can be constructed with 3 IC packages each of
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Question 100
When numbers, letters or words are represented by a special group of symbols, this process is called
A. decoding
B. encoding
C. digitizing
D. inverting
Question 101
The output sum of two decimal digits can be represented in
A. gray code
B. excess-3
C. bcd
D. hexadecimal
Question 102
The addition of two decimal digits in BCD can be done through
A. bcd adder
B. full adder
C. ripple carry adder
D. carry look ahead
Question 103
The decimal equivalent of the excess-3 number 110010100011.01110101 is
A. 970.42
B. 1253.75
C. 861.75
D. 1132.87
Question 104
3 bits full adder contains
A. 3 combinational inputs
B. 4 combinational inputs
C. 6 combinational inputs
D. 8 combinational inputs
Question 105
The simplified expression of full adder carry is
A. c = xy+xz+yz
B. c = xy+xz
C. c = xy+yz
D. c = x+y+z
Question 106
The expression for Absorption law is given by
A. a + ab = a
B. a + ab = b
C. ab + aa’ = a
D. a + b = b + a
Question 107
Complement of F’ gives back
A. f’
B. f
C. ff
D. ff’
Question 108
According to boolean law: A + 1 = ?
A. 1
B. a
C. a’
Question 109
Decimal digit in BCD can be represented by
A. 1 input line
B. 2 input lines
C. 3 input lines
D. 4 input lines
Question 110
The involution of A is equal to
A. a
B. a’
C. 1
Question 111
The number of logic gates and the way of their interconnections can be classified as
A. logical network
B. system network
C. circuit network
D. gate network
Question 112
DeMorgan’s theorem states that
A. (ab)’ = a’ + b’
B. (a + b)’ = a’ * b
C. a’ + b’ = a’b’
D. (ab)’ = a’ + b
Question 113
Complement of the expression A’B + CD’ is
A. (a’ + b)(c’ + d)
B. (a + b’)(c’ + d)
C. (a’ + b)(c’ + d)
D. (a + b’)(c + d’)
Question 114
It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of
A. inputs
B. outputs
C. selection lines
D. enable lines
Question 115
6 MULTIPLEXER
A. to apply vcc
B. to connect ground
C. to active the entire chip
D. to active one half of the chip
Question 116
The boolean function A + BC is a reduced form of
A. ab + bc
B. (a + b)(a + c)
C. a’b + ab’c
D. (a + c)b
Question 117
One multiplexer can take the place of
A. several ssi logic gates
B. combinational logic circuits
C. several ex-nor gates
D. several ssi logic gates or combinational logic circuits
Question 118
A is a circuit with only one output but can have multiple inputs.
A. logic gate
B. truth table
C. binary circuit
D. boolean circuit
Question 119
A digital multiplexer is a combinational circuit that selects
A. one digital information from several sources and transmits the selected one
B. many digital information and convert them into one
C. many decimal inputs and transmits the selected information
D. many decimal outputs and accepts the selected information
Question 120
There are 5 universal gates.
A. TRUE
B. FALSE
Question 121
If the number of n selected input lines is equal to 2^m then it requires select lines.
A. 2
B. m
C. n
D. 2n
Question 122
The Output is LOW if any one of the inputs is HIGH in case of a gate.
A. nor
B. nand
C. or
D. and
Question 123
The complement of the input given is obtained in case of:
A. nor
B. and+nor
C. not
D. ex-or
Question 124
A basic multiplexer principle can be demonstrated through the use of a
A. single-pole relay
B. dpdt switch
C. rotary switch
D. linear stepper
Question 125
How many AND gates are required to realize the following expression Y=AB+BC?
A. 4
B. 8
C. 1
D. 2
Question 126
Number of outputs in a half adder
A. 1
B. 2
C. 3
Question 127
The gate is an OR gate followed by a NOT gate.
A. nand
B. exor
C. nor
D. exnor
Question 128
The expression of a NAND gate is
A. a.b
B. a’b+ab’
C. (a.b)’
D. (a+b)’
Question 129
Which of the following correctly describes the distributive law.
A. ( a+b)(c+d)=ab+cd
B. (a+b).c=ac+bc
C. (ab)(a+b)=ab
D. (a.b)c=ac.ab
Question 130
The logical sum of two or more logical product terms is called
A. sop
B. pos
C. or operation
D. nand operation
Question 131
The expression Y=(A+B)(B+C)(C+A) shows the operation.
A. and
B. pos
C. sop
D. nand
Question 132
In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is
A. x0
B. x1
C. x2
D. x3
Question 133
The canonical sum of product form of the function y(A,B) = A + B is
A. ab + bb + a’a
B. ab + ab’ + a’b
C. ba + ba’ + a’b’
D. ab’ + a’b + a’b’
Question 134
A variable on its own or in its complemented form is known as a
A. product term
B. literal
C. sum term
D. word
Question 135
The enable input is also known as
A. select input
B. decoded input
C. strobe
D. sink
Question 136
The word demultiplex means
A. one into many
B. many into one
C. distributor
D. one into many as well as distributor
Question 137
Maxterm is the sum of of the corresponding Minterm with its literal complemented.
A. terms
B. words
C. numbers
D. nibble
Question 138
Canonical form is a unique way of representing
A. sop
B. minterm
C. boolean expressions
D. pos
Question 139
There are Minterms for 3 variables (a, b, c).
A. 0
B. 2
C. 8
D. 1
Question 140
expressions can be implemented using either (1) 2-level AND- OR logic circuits or (2) 2-level NAND logic circuits.
A. pos
B. literals
C. sop
D. pos
Question 141
In a multiplexer the output depends on its
A. data inputs
B. select inputs
C. select outputs
D. enable pin
Question 142
There are cells in a 4-variable K- map.
A. 12
B. 16
C. 18
D. 8
Question 143
In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be
A. y0
B. y1
C. y2
D. y3
Question 144
In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be
A. y0
B. y1
C. y2
D. y3
Question 145
How many select lines are required for a 1- to-8 demultiplexer?
A. 2
B. 3
C. 4
D. 5
Question 146
How many AND gates are required for a 1- to-8 multiplexer?
A. 2
B. 6
C. 8
D. 5
Question 147
All the comparisons made by comparator is done using
A. 1 circuit
B. 2 circuits
C. 3 circuits
D. 4 circuits
Question 148
One that is not the outcome of magnitude comparator is
A. a > b
B. a – b
C. a < b
D. a = b
Question 149
If two numbers are not equal then binary variable will be
A. 0
B. 1
C. a
D. b
Question 150
How many inputs are required for a digital comparator?
A. 1
B. 2
C. 3
D. 4
Question 151
The parallel outputs of a counter circuit represent the
A. parallel data word
B. clock frequency
C. counter modulus
D. clock count
Question 152
Ring shift and Johnson counters are
A. synchronous counters
B. asynchronous counters
C. true binary counters
D. synchronous and true binary counters
Question 153
In a comparator, if we get input as A>B then the output will be
A. 1
B. 0
C. a
D. b
Question 154
Comparators are used in
A. memory
B. cpu
C. motherboard
D. hard drive
Question 155
A circuit that compares two numbers and determine their magnitude is called
A. height comparator
B. size comparator
C. comparator
D. magnitude comparator
Question 156
A procedure that specifies finite set of steps is called
A. algorithm
B. flow chart
C. chart
D. venn diagram
Question 157
A 74HC195 4-bit parallel access shift register can be used for
A. serial in/serial out operation
B. serial in/parallel out operation
C. parallel in/serial out operation
D. all of the mentioned
Question 158
An identify comparator is defined as a digital comparator which has
A. only one output terminal
B. two output terminals
C. three output terminals
D. no output terminal
Question 159
A magnitude comparator is defined as a digital comparator which has
A. only one output terminal
B. two output terminals
C. three output terminals
D. no output terminal
Question 160
Another way to connect devices to a shared data bus is to use a
A. circulating gate
B. transceiver
C. bidirectional encoder
D. strobed latch
Question 161
The purpose of a Digital Comparator is
A. to convert analog input into digital
B. to create different outputs
C. to add a set of different numbers
D. to compare a set of variables or unknown numbers
Question 162
The full form of SIPO is
A. serial-in parallel-out
B. parallel-in serial-out
C. serial-in serial-out
D. serial-in peripheral-out
Question 163
TTL 74LS85 is a
A. 1-bit digital comparator
B. 4-bit magnitude comparator
C. 8-bit magnitude comparator
D. 8-bit word comparator
Question 164
4 to 1 MUX would have
A. 2 inputs
B. 3 inputs
C. 4 inputs
D. 5 inputs
Question 165
A combinational circuit that selects one from many inputs are
A. encoder
B. decoder
C. demultiplexer
D. multiplexer
Question 166
What is meant by parallel load of a shift register?
A. all ffs are preset with data
B. each ff is loaded with data, one at a time
C. parallel shifting of data
D. all ffs are set with data
Question 167
4 to 1 MUX would have
A. 1 output
B. 2 outputs
C. 3 outputs
D. 4 outputs
Question 168
The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains
A. 1110
B. 1
C. 101
D. 110
Question 169
The inputs/outputs of an analog multiplexer/demultiplexer are
A. bidirectional
B. unidirectional
C. even parity
D. binary-coded decimal
Question 170
If enable input is high then the multiplexer is
A. enable
B. disable
C. saturation
D. high impedance
Question 171
A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains
A. 0
B. 1111
C. 111
D. 1000
Question 172
What is data routing in a multiplexer?
A. it spreads the information to the control unit
B. it can be used to route data from one of several source to destination
C. it is an application of multiplexer
D. both it can be used to route data and it is an application of multiplexer
Question 173
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms
Question 174
An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of
A. 16 us
B. 8 us
C. 4 us
D. 2 us
Question 175
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
A. 1101
B. 111
C. 1
D. 1110
Question 176
If we record any music in any recorder, such types of process is called
A. multiplexing
B. encoding
C. decoding
D. demultiplexing
Question 177
How is an strobe signal used when serially loading a shift register?
A. to turn the register on and off
B. to control the number of clocks
C. to determine which output qs are used
D. to determine the ffs that will be used
Question 178
Can an encoder be called as multiplexer?
A. no
B. yes
C. sometimes
D. never
Question 179
The primary purpose of a three-state buffer is usually
A. to provide isolation between the input device and the data bus
B. to provide the sink or source current required by any device connected to its output without loading down the output device
C. temporary data storage
D. to control data flow
Question 180
A latch is an example of a
A. monostable multivibrator
B. astable multivibrator
C. bistable multivibrator
D. 555 timer
Question 181
One example of the use of an S-R flip-flop is as
A. transition pulse generator
B. racer
C. switch debouncer
D. astable oscillator
Question 182
Latch is a device with
A. one stable state
B. two stable state
C. three stable state
D. infinite stable states
Question 183
Why latches are called a memory devices?
A. it has capability to stare 8 bits of data
B. it has internal memory of 4 bit
C. it can store one bit of data
D. it can store infinite amount of data
Question 184
When both inputs of a J-K flip-flop cycle, the output will
A. be invalid
B. change
C. not change
D. toggle
Question 185
Two stable states of latches are
A. astable & monostable
B. low input & high output
C. high output & low output
D. low output & high input
Question 186
A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
A. and or or gates
B. xor or xnor gates
C. nor or nand gates
D. and or nor gates
Question 187
The full form of SR is
A. system rated
B. set reset
C. set ready
D. set rated
Question 188
The SR latch consists of
A. 1 input
B. 2 inputs
C. 3 inputs
D. 4 inputs
Question 189
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
A. combinational circuits
B. sequential circuits
C. latches
D. flip-flops
Question 190
The outputs of SR latch are
A. x and y
B. a and b
C. s and r
D. q and q’
Question 191
The NAND latch works when both inputs are
A. 1
B. 0
C. inverted
D. don’t cares
Question 192
The first step of analysis procedure of SR latch is to
A. label inputs
B. label outputs
C. label states
D. label tables
Question 193
The inputs of SR latch are
A. x and y
B. a and b
C. s and r
D. j and k
Question 194
The sequential circuit is also called
A. flip-flop
B. latch
C. strobe
D. adder
Question 195
When a high is applied to the Set line of an SR latch, then
A. q output goes high
B. q’ output goes high
C. q output goes low
D. both q and q’ go high
Question 196
The basic latch consists of
A. two inverters
B. two comparators
C. two amplifiers
D. two adders
Question 197
When both inputs of SR latches are low, the latch
A. q output goes high
B. q’ output goes high
C. it remains in its previously set or reset state
D. it goes to its next set or reset state
Question 198
In S-R flip-flop, if Q = 0 the output is said to be
A. set
B. reset
C. previous state
D. current state
Question 199
When both inputs of SR latches are high, the latch goes
A. unstable
B. stable
C. metastable
D. bistable
Question 200
The output of latches will remain in set/reset untill
A. the trigger pulse is given to change the state
B. any pulse given to go into previous state
C. they don’t get any pulse more
D. the pulse is edge-triggered
Question 201
is used to drive high capacitance load.
A. single polar capability
B. bipolar capability
C. tripolar capability
D. bi and tri polar capability
Question 202
Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have:
A. a greater current/voltage capability than an ordinary logic circuit
B. greater input current/voltage capability than an ordinary logic circuit
C. a smaller output current/voltage capability than an ordinary logic
D. greater the input and output current/voltage capability than an ordinary logic circuit
Question 203
As the temperature is increased, storage time
A. halved
B. doubled
C. does not change
D. tripled
Question 204
Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS.
A. six, eight
B. eight, six
C. five, six
D. six, five
Question 205
What must be done to interface TTL to CMOS?
A. a dropping resistor must be used on the cmos of 12 v supply to reduce it to 5 v for the ttl
B. as long as the cmos supply voltage is 5 v they can be interfaced (however, the fan- out of the ttl is limited to five cmos gates)
C. a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates
D. a pull-up resistor must be used between the ttl output-cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node
Question 206
Output values of Moore type FSM are determined by its
A. input values
B. output values
C. clock input
D. current state
Question 207
3 CYCLES AND RACES, STATE REDUCTION
A. 1
B. 2
C. 3
D. 4
Question 208
Memory is a/an
A. device to collect data from other computer
B. block of data to keep data separately
C. indispensable part of computer
D. device to connect through all over the world
Question 209
The instruction used in a program for executing them is stored in the
A. cpu
B. control unit
C. memory
D. microprocessor
Question 210
A register file holds
A. a large number of word of information
B. a small number of word of information
C. a large number of programs
D. a modest number of words of information
Question 211
The very first computer memory consisted of
A. a small display
B. a large memory storage equipment
C. an automatic keyboard input
D. an automatic mouse input
Question 212
A flip flop stores
A. 10 bit of information
B. 1 bit of information
C. 2 bit of information
D. 3-bit information
Question 213
Moore machine has states than a mealy machine.
A. fewer
B. more
C. equal
D. negligible
Question 214
A large memory is compressed into a small one by using
A. lsi semiconductor
B. vlsi semiconductor
C. cdr semiconductor
D. ssi semiconductor
Question 215
State transition happens in every clock cycle.
A. once
B. twice
C. thrice
D. four times
Question 216
The full form of PLD is
A. programmable large device
B. programmable long device
C. programmable logic device
D. programmable lengthy device
Question 217
VLSI chip utilizes
A. nmos
B. cmos
C. bjt
D. all of the mentioned
Question 218
In digital logic, a counter is a device which
A. counts the number of outputs
B. stores the number of times a particular event or process has occurred
C. stores the number of times a clock pulse rises and falls
D. counts the number of inputs
Question 219
CD-ROM refers to
A. floppy disk
B. compact disk-read only memory
C. compressed disk-read only memory
D. compressed disk- random access memory
Question 220
A counter circuit is usually constructed of
A. a number of latches connected in cascade form
B. a number of nand gates connected in cascade form
C. a number of flip-flops connected in cascade
D. a number of nor gates connected in cascade form
Question 221
Data stored in an electronic memory cell can be accessed at random and on demand
A. erom
B. ram
C. prom
D. eeprom
Question 222
A decimal counter has states.
A. 5
B. 10
C. 15
D. 20
Question 223
A ROM is defined as
A. read out memory
B. read once memory
C. read only memory
D. read one memory
Question 224
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
A. 0 to 2n
B. 0 to 2n + 1
C. 0 to 2n – 1 d) 0 to 2n+1/2
Question 225
ROM has the capability to perform
A. write operation only
B. read operation only
C. both write and read operation
D. erase operation
Question 226
Three decade counter would have
A. 2 bcd counters
B. 3 bcd counters
C. 4 bcd counters
D. 5 bcd counters
Question 227
BCD counter is also known as
A. parallel counter
B. decade counter
C. synchronous counter
D. vlsi counter
Question 228
The ROM is a
A. sequential circuit
B. combinational circuit
C. magnetic circuit
D. static circuit
Question 229
ROM is made up of
A. nand and or gates
B. nor and decoder
C. decoder and or gates
D. nand and decoder
Question 230
Why are ROMs called non-volatile memory?
A. they lose memory when power is removed
B. they do not lose memory when power is removed
C. they lose memory when power is supplied
D. they do not lose memory when power is supplied
Question 231
Propagation delay is defined as
A. the time taken for the output of a gate to change after the inputs have changed
B. the time taken for the input of a gate to change after the outputs have changed
C. the time taken for the input of a gate to change after the intermediates have changed
D. the time taken for the output of a gate to change after the intermediates have changed
Question 232
In ROM, each bit is a combination of the address variables is called
A. memory unit
B. storage class
C. data word
D. address
Question 233
Which is not a removable drive?
A. zip
B. hard disk
C. super disk
D. jaz
Question 234
Propagation delay times can be divided as
A. t(plh) and t(lph)
B. t(lph) and t(phl)
C. t(plh) and t(phl)
D. t(hpl) and t(lph)
Question 235
In ROM, each bit combination that comes out of the output lines is called
A. memory unit
B. storage class
C. data word
D. address
Question 236
Power Dissipation in DIC is expressed in
A. watts or kilowatts
B. milliwatts or nanowatts
C. db
D. mdb
Question 237
VLSI chip utilizes
A. nmos
B. cmos
C. bjt
D. all of the mentioned
Question 238
Fan-in is defined as
A. the number of outputs connected to gate without any degradation in the voltage levels
B. the number of inputs connected to gate without any degradation in the voltage levels
C. the number of outputs connected to gate with degradation in the voltage levels
D. the number of inputs connected to gate with degradation in the voltage levels
Question 239
The time from the beginning of a read cycle to the end of tACS/tAA is called as
A. write enable time
B. data hold
C. read cycle time
D. access time
Question 240
The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as
A. noise margin
B. noise immunity
C. white noise
D. signal to noise ratio
Question 241
The full form of ECL is
A. emitter-collector logic
B. emitter-complementary logic
C. emitter-coupled logic
D. emitter-cored logic
Question 242
The full form of CML is
A. complementary mode logic
B. current mode logic
C. collector mode logic
D. collector mixed logic
Question 243
PROMs are available in
A. bipolar and mosfet technologies
B. mosfet and fet technologies
C. fet and bipolar technologies
D. mos and bipolar technologies
Question 244
In an ECL the output is taken from
A. emitter
B. base
C. collector
D. junction of emitter and base
Question 245
The ECL behaves as
A. not gate
B. nor gate
C. nand gate
D. and gate
Question 246
In ECL the fanout capability is
A. high
B. low
C. zero
D. sometimes high and sometimes low
Question 247
ECL’s major disadvantage is that
A. it requires more power
B. it’s fanout capability is high
C. it creates more noise
D. it is slow
Question 248
The full form of SCFL is
A. source-collector logic
B. source-coupled logic
C. source-complementary logic
D. source cored logic
Question 249
The equivalent of emitter-coupled logic made out of FETs is called
A. cml
B. scfl
C. fecl
D. efcl
Question 250
ECL was invented in by
A. 1956, baker clamp
B. 1976, james r. biard
C. 1956, hannon s. yourke
D. 1976, yourke
Question 251
At the time of invention, an ECL was called as
A. source-coupled logic
B. current mode logic
C. current-steering logic
D. emitter-coupled logic
Question 252
The ECL circuits usually operates with
A. negative voltage
B. positive voltage
C. grounded voltage
D. high voltage
Question 253
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of
A. ecl
B. vecl
C. pecl
D. lecl
Question 254
Fusing process is
A. reversible
B. irreversible
C. synchronous
D. asynchronous
Question 255
The cell type used inside a PROM is
A. link cells
B. metal cells
C. fuse cells
D. electric cells
Question 256
Metal links are made up of
A. polycrystalline
B. magnesium sulphide
C. nichrome
D. silicon dioxide
Question 257
EPROM uses an array of
A. p-channel enhancement type mosfet
B. n-channel enhancement type mosfet
C. p-channel depletion type mosfet
D. n-channel depletion type mosfet
Question 258
The EPROM was invented by
A. wen tsing chow
B. dov frohman
C. luis o brian
D. j p longwell
Question 259
Address decoding for dynamic memory chip control may also be used for
A. chip selection and address location
B. read and write control
C. controlling refresh circuits
D. memory mapping
Question 260
Which of the following describes the action of storing a bit of data in a mask ROM?
A. a 0 is stored by connecting the gate of a mos cell to the address line
B. a 0 is stored in a bipolar cell by shorting the base connection to the address line
C. a 1 is stored by connecting the gate of a mos cell to the address line
D. a 1 is stored in a bipolar cell by opening the base connection to the address line
Question 261
The check sum method of testing a ROM
A. allows data errors to be pinpointed to a specific memory location
B. provides a means for locating and correcting data errors in specific memory locations
C. indicates if the data in more than one memory location is incorrect
D. simply indicates that the contents of the rom are incorrect
Question 262
The initial values in all the cells of an EPROM is
A. 0
B. 1
C. both 0 and 1
D. alternate 0s and 1s
Question 263
To store 0 in such a cell, the floating point must be
A. reprogrammed
B. restarted
C. charged
D. power off
Question 264
To read from the memory, the select input and the power down/program input must be
A. high
B. low
C. sometimes high and sometimes low
D. alternate high and low
Question 265
ROMs retain data when
A. power is on
B. power is off
C. system is down
D. all of the mentioned
Question 266
When a RAM module passes the checker board test it is
A. able to read and write only 0s
B. faulty
C. probably good
D. able to read and write only 1s
Question 267
What is access time?
A. the time taken to move a stored word from one bit to other bits after applying the address bits
B. the time taken to write a word after applying the address bits
C. the time taken to read a stored word after applying the address bits
D. the time taken to erase a stored word after applying the address bits
Question 268
The chip by which both the operation of read and write is performed
A. ram
B. rom
C. prom
D. eprom
Question 269
RAM is also known as
A. rwm
B. mbr
C. mar
D. rom
Question 270
If a RAM chip has n address input lines then it can access memory locations upto
A. 2(n-1)
B. 2(n+1)
C. 2n
D. 22n
Question 271
The n-bit address is placed in the
A. mbr
B. mar
C. ram
D. rom
Question 272
Computers invariably use RAM for
A. high complexity
B. high resolution
C. high speed main memory
D. high flexibility
Question 273
Static RAM employs
A. bjt or mosfet
B. fet or jfet
C. capacitor or bjt
D. bjt or mos
Question 274
Dynamic RAM employs
A. capacitor or mosfet
B. fet or jfet
C. capacitor or bjt
D. bjt or mos
Question 275
The data written in flip-flop remains stored as long as
A. d.c. power is supplied
B. d.c. power is removed
C. a.c. power is supplied
D. a.c. power is removed
Question 276
The first step in the design of memory decoder is
A. selection of a eprom
B. selection of a ram
C. address assignment
D. data insertion
Question 277
How many address bits are required to select memory location in Memory decoder?
A. 4 kb
B. 8 kb
C. 12 kb
D. 16 kb
Question 278
How memory expansion is done?
A. by increasing the supply voltage of the memory ics
B. by decreasing the supply voltage of the memory ics
C. by connecting memory ics together
D. by separating memory ics
Question 279
IC 4116 is organised as
A. 512 * 4
B. 16 * 1
C. 32 * 4
D. 64 * 2
Question 280
The full form of PLD is
A. programmable load devices
B. programmable logic data
C. programmable logic devices
D. programmable loaded devices
Question 281
PLD contains a large number of
A. flip-flops
B. gates
C. registers
D. all of the mentioned
Question 282
Logic circuits can also be designed using
A. ram
B. rom
C. pld
D. pla
Question 283
PAL refers to
A. programmable array loaded
B. programmable logic array
C. programmable array logic
D. programmable and logic
Question 284
Outputs of the AND gate in PLD is known as
A. input lines
B. output lines
C. strobe lines
D. control lines
Question 285
PLA contains
A. and and or arrays
B. nand and or arrays
C. not and and arrays
D. nor and or arrays
Question 286
PLA is used to implement
A. a complex sequential circuit
B. a simple sequential circuit
C. a complex combinational circuit
D. a simple combinational circuit
Question 287
A PLA is similar to a ROM in concept except that
A. it hasn’t capability to read only
B. it hasn’t capability to read or write operation
C. it doesn’t provide full decoding to the variables
D. it hasn’t capability to write only
Question 288
The complex programmable logic device contains several PLD blocks and
A. a language compiler
B. and/or arrays
C. global interconnection matrix
D. field-programmable switches
Question 289
The difference between a PAL & a PLA is
A. pals and plas are the same thing
B. the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane
C. the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane
D. the pal has more possible product terms than the pla
Question 290
If a PAL has been programmed once
A. its logic capacity is lost
B. its outputs are only active high
C. its outputs are only active low
D. it cannot be reprogrammed
Question 291
The FPGA refers to
A. first programmable gate array
B. field programmable gate array
C. first program gate array
D. field program gate array
Question 292
The full form of VLSI is
A. very long single integration
B. very least scale integration
C. very large scale integration
D. very long scale integration
Question 293
In FPGA, vertical and horizontal directions are separated by
A. a line
B. a channel
C. a strobe
D. a flip-flop
Question 294
Applications of PLAs are
A. registered pals
B. configurable pals
C. pal programming
D. all of the mentioned
Question 295
CMOS refers to
A. continuous metal oxide semiconductor
B. complementary metal oxide semiconductor
C. centred metal oxide semiconductor
D. concrete metal oxide semiconductor