Digital System Projects Using HDL MCQs : This section focuses on the "Digital System Projects Using HDL". These Multiple Choice Questions (MCQs) should be practiced to improve the Digital System Projects Using HDL skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
What does the major block of an HDL code emulation of a keypad include?
A. A sequencer
B. A clock
C. A multiplexer
D. A ring counter
Why should a real hardware functional test be performed on the HDL stepper motor design?
A. To check the speed of the software
B. To check the current levels in the motor
C. To check the voltage levels of the real outputs
D. To provide a fully operational system
The accuracy of the frequency counter depends on the:
A. system clock frequency.
B. number of displayed digits.
C. sampling rate.
D. display update rate.
In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
A. It goes HIGH.
B. It goes LOW.
C. It goes to Hi-Z.
D. It goes to 1111H.
Which is not a step in strategic planning for HDL development?
A. There must be a way to test each piece.
B. Each block must fit together to make up the whole system.
C. The names of each input and output must be known.
D. The exact operation of each block must be thoroughly defined and understood.
For the frequency counter, which is not a control signal from the control and timing block?
What does the ring counter in the HDL keypad application do when a key is pressed?
A. Count to find the row
C. Count to find the column
D. Start the D flip-flop
In the digital clock project, the purpose of the frequency prescaler is to:
A. find the basic frequency.
B. transform a 60 pps input to a 1 pps timing signal.
C. prevent the clock from exceeding 12:59:59.
D. allow the BCD display to have a value from 00–59.
In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?
In an HDL application of a stepper motor, after an up/down counter is built what is done next?
A. Build the sequencer
B. Test it on a simulator
C. Test the decoder
D. Design an intermediate integer variable
In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
In the frequency counter, when is the new count stored in the display register?
A. After disabling the counter
B. When the count buffer is full
C. After the sample interval is set
D. When the timing and control block has put it there
In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?
A. 1 pulse per minute
B. 6 pulses per minute
C. 10 pulses per minute
D. 1 pulse per hour
In a digital clock application, the basic frequency must be divided down to:
A. 1 Hz.
B. 60 Hz.
C. 100 Hz.
D. 1000 Hz.
How is the output frequency related to the sampling interval of a frequency counter?
A. Directly with the sampling interval
B. Inversely with the sampling interval
C. More precision with longer sampling interval
D. Less precision with longer sampling interval
When designing an HDL digital system, which is the worst mistake one can make?
A. Concluding that a fundamental block works perfectly
B. Failing to provide proper documentation
C. Adding blocks of code prior to testing them
D. Overlooking a possible VARIABLE
Which is not a step used to define the scope of an HDL project?
A. Are the inputs and outputs active HIGH or active LOW?
B. A clear vision of how to make each block work
C. What are the speed requirements?
D. How many bits of data are needed?
In the digital clock project, when does the PM indicator go high?
B. Going from 11:59:59 to 12:00:00
C. Going from 12:59:59 to 01:00:00
D. On the falling edge of the clock after enable goes high
In the keypad application, what does the data signal define?
A. The row and column encoded data
B. The ring encoded data
C. The freeze locator data
D. The ring counter data
List three basic blocks in the digital clock project.
A. MOD-60, MOD-12 counters
B. MOD-5, MOD-10, MOD-12 counters
C. MOD-60, MOD-10 counters
D. MOD-6, MOD-12, and MOD-10 counters
In the keypad application, what does the preset state of the ring counter define?
A. The proper output of the column encoder
B. The NANDing of the rows
C. The NANDing of the columns
D. The proper output of the row encoder
In an HDL stepper motor design, why is there more than one mode?
A. To change the speed of the stepper motor
B. To change the direction of the stepper motor
C. To direct drive the stepper motor
D. All of the above
What are two ways to remember the current state of a counter in VHDL?
A. With FUNCTIONS and PROCESS
B. With counters and timers
C. With SIGNAL and VARIABLE
D. With bit types
In a frequency counter, what happens at high frequencies when the sampling interval is too long?
A. The counter works fine.
B. The counter undercounts the frequency.
C. The measurement is less precise.
D. The counter overflows.
Which is not a step that should be followed in project management?
A. Overall definition
B. System documentation
C. Synthesis and testing
D. System integration
In the frequency counter, what is the function of the Schmitt trigger circuit?
A. To reduce input noise
B. To condition the input signal
C. To convert non-square waveforms
D. To provide a usable signal to the display unit
What must a stepper motor HDL application include?
A. Variables and processes
B. Types and bits
C. Counters and decoders
D. Sequencers and multiplexers
In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?
Which is not a major block of an HDL frequency counter?
A. Display register
C. Timing and control unit
D. Bit shifter
In the digital clock project, what type of counter is used to count to 59 seconds?
D. BCD followed by a MOD-6