Field Effect Transistors (FET) MCQs : This section focuses on the "Field Effect Transistors (FET)". These Multiple Choice Questions (MCQs) should be practiced to improve the Field Effect Transistors (FET) skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
The type of bias most often used with E-MOSFET circuits is:
A. constant current
D. zero biasing
Which component is considered to be an "OFF" device?
A MOSFET has how many terminals?
A. 2 or 3
D. 3 or 4
In the constant-current region, how will the IDS change in an n-channel JFET?
A. As VGS decreases ID decreases.
B. As VGS increases ID increases.
C. As VGS decreases ID remains constant.
D. As VGS increases ID remains constant.
With the E-MOSFET, when gate input voltage is zero, drain current is:
A. at saturation
D. widening the channel
Which type of JFET bias requires a negative supply voltage?
D. voltage divider
With a 30-volt VDD, and an 8-kilohm drain resistor, what is the E-MOSFET Q point voltage, with ID = 3 mA?
A. 6 V
B. 10 V
C. 24 V
D. 30 V
Junction Field Effect Transistors (JFET) contain how many diodes?
When the JFET is no longer able to control the current, this point is called the:
A. breakdown region
B. depletion region
C. saturation point
D. pinch-off region
The common-source JFET amplifier has:
A. a very high input impedance and a relatively low voltage gain
B. a high input impedance and a very high voltage gain
C. a high input impedance and a voltage gain less than 1
D. no voltage gain
How will a D-MOSFET input impedance change with signal frequency?
A. As frequency increases input impedance increases.
B. As frequency increases input impedance is constant.
C. As frequency decreases input impedance increases.
D. As frequency decreases input impedance is constant.
When VGS = 0 V, a JFET is:
B. an analog device
C. an open switch
D. cut off
Which JFET configuration would connect a high-resistance signal source to a low-resistance load?
A. source follower
The overall input capacitance of a dual-gate D-MOSFET is lower because the devices are usually connected:
A. in parallel
B. with separate insulation
C. with separate inputs
D. in series
IDSS can be defined as:
A. the minimum possible drain current
B. the maximum possible current with VGS held at –4 V
C. the maximum possible current with VGS held at 0 V
D. the maximum drain current with the source shorted
When applied input voltage varies the resistance of a channel, the result is called:
D. field effect
When an input signal reduces the channel size, the process is called:
B. substrate connecting
C. gate charge
When is a vertical channel E-MOSFET used?
A. for high frequencies
B. for high voltages
C. for high currents
D. for high resistances
D-MOSFETs are sometimes used in series to construct a cascode high-frequency amplifier to overcome the loss of:
A. low output impedance
B. capacitive reactance
C. high input impedance
D. inductive reactance
JFET terminal "legs" are connections to the drain, the gate, and the:
When an input delta of 2 V produces a transconductance of 1.5 mS, what is the drain current delta?
A. 666 mA
B. 3 mA
C. 0.75 mA
D. 0.5 mA
When not in use, MOSFET pins are kept at the same potential through the use of:
A. shipping foil
B. nonconductive foam
C. conductive foam
D. a wrist strap
How will electrons flow through a p-channel JFET?
A. from source to drain
B. from source to gate
C. from drain to gate
D. from drain to source
The transconductance curve of a JFET is a graph of:
A. IS versus VDS
B. IC versus VCE
C. ID versus VGS
D. ID × RDS
With a JFET, a ratio of output current change against an input voltage change is called:
A "U" shaped, opposite-polarity material built near a JFET-channel center is called the:
D. heat sink
In an n-channel JFET, what will happen at the pinch-off voltage?
A. the value of VDS at which further increases in VDS will cause no further increase in ID
B. the value of VGS at which further decreases in VGS will cause no further increases in ID
C. the value of VDG at which further decreases in VDG will cause no further increases in ID
D. the value of VDS at which further increases in VGS will cause no further increases in ID
A very simple bias for a D-MOSFET is called:
A. self biasing
B. gate biasing
C. zero biasing
D. voltage-divider biasing
What is the input impedance of a common-gate configured JFET?
A. very low
D. very high