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Flip-Flops and Timers MCQ Questions & Answers

Flip-Flops and Timers MCQs : This section focuses on the "Flip-Flops and Timers". These Multiple Choice Questions (MCQs) should be practiced to improve the Flip-Flops and Timers skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.

Question 1

The truth table for an S-R flip-flop has how many VALID entries?

A. 3
B. 1
C. 4
D. 2

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Question 2

What is the significance of the J and K terminals on the J-K flip-flop?

A. There is no known significance in their designations.
B. The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH.
C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
D. All of the other letters of the alphabet are already in use.

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Question 3

A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

A. AND or OR gates
B. XOR or XNOR gates
C. NOR or NAND gates
D. AND or NOR gates

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Question 4

When both inputs of a J-K flip-flop cycle, the output will:

A. be invalid
B. not change
C. change
D. toggle

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Question 5

What is another name for a one-shot?

A. monostable
B. bistable
C. astable
D. tristable

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Question 6

An astable multivibrator is a circuit that:

A. has two stable states
B. is free-running
C. produces a continuous output signal
D. is free-running and produces a continuous output signal

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Question 7

The 555 timer can be used in which of the following configurations?

A. astable, monostable
B. monostable, bistable
C. astable, toggled
D. bistable, tristable

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Question 8

What is one disadvantage of an S-R flip-flop?

A. It has no Enable input.
B. It has a RACE condition.
C. It has no clock input.
D. It has only a single output.

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Question 9

One example of the use of an S-R flip-flop is as a(n):

A. transition pulse generator
B. astable oscillator
C. racer
D. switch debouncer

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Question 10

Which of the following is correct for a gated D-type flip-flop?

A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
B. The output complement follows the input when enabled.
C. Only one of the inputs can be HIGH at a time.
D. The output toggles if one of the inputs is held HIGH.

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Question 11

If both inputs of an S-R NAND latch are LOW, what will happen to the output?

A. The output would become unpredictable.
B. The output will toggle.
C. The output will reset.
D. No change will occur in the output.

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Question 12

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A. asynchronous operation
B. low input voltages
C. gate impedance
D. cross coupling

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Question 13

Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

A. If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

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