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Flip-Flops MCQ Questions & Answers

Flip-Flops MCQs : This section focuses on the "Flip-Flops". These Multiple Choice Questions (MCQs) should be practiced to improve the Flip-Flops skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.




Question 1

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

A. 16
B. 8
C. 4
D. 2

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Question 2

In VHDL, how is each instance of a component addressed?

A. A name followed by a colon and the name of the library primitive
B. A name followed by a semicolon and the component type
C. A name followed by the library being used
D. A name followed by the component library number

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Question 3

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

A. constantly LOW
B. constantly HIGH
C. a 20 kHz square wave
D. a 10 kHz square wave

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Question 4

Edge-triggered flip-flops must have:

A. very fast response times.
B. at least two inputs to handle rising and falling edges.
C. a pulse transition detector.
D. active-LOW inputs and complemented outputs.

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Question 5

On a master-slave flip-flop, when is the master enabled?

A. when the gate is LOW
B. when the gate is HIGH
C. both of the above
D. neither of the above

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Question 6

How many flip-flops are required to produce a divide-by-128 device?

A. 1
B. 4
C. 6
D. 7

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Question 7

The output of a gated S-R flip-flop changes only if the:

A. flip-flop is set
B. control input data has changed
C. flip-flop is reset
D. input data has no change

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Question 8

What is the difference between the 7476 and the 74LS76?

A. the 7476 is master-slave, the 74LS76 is master-slave
B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
C. the 7476 is edge-triggered, the 74LS76 is master-slave
D. the 7476 is master-slave, the 74LS76 is edge-triggered

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Question 9

If an input is activated by a signal transition, it is ________.

A. edge-triggered
B. toggle triggered
C. clock triggered
D. noise triggered

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Question 10

With regard to a D latch, ________.

A. the Q output follows the D input when EN is LOW
B. the Q output is opposite the D input when EN is LOW
C. the Q output follows the D input when EN is HIGH
D. the Q output is HIGH regardless of EN's input state

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Question 11

Which is not an Altera primitive port identifier?

A. clk
B. ena
C. clr
D. prn

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Question 12

Which of the following best describes the action of pulse-triggered FF's?

A. The clock and the S-R inputs must be pulse shaped.
B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
C. A pulse on the clock transfers data from input to output.
D. The synchronous inputs must be pulsed.

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Question 13

Which is not a real advantage of HDL?

A. Using higher levels of abstraction
B. Tailoring components to exactly fit the needs of the project
C. The use of graphical tools
D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

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Question 14

Edge-triggered flip-flops must have:

A. very fast response times
B. at least two inputs to handle rising and falling edges
C. positive edge-detection circuits
D. negative edge-detection circuits

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Question 15

What does the triangle on the clock input of a J-K flip-flop mean?

A. level enabled
B. edge-triggered

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Question 16

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

A. active-HIGH
B. active-LOW

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Question 17

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

A. edge-detection circuit.
B. NOR latch.
C. NAND latch.
D. pulse-steering circuit.

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Question 18

Which of the following describes the operation of a positive edge-triggered D flip-flop?

A. If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

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Question 19

An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

A. HIGHs are applied simultaneously to both inputs S and R
B. LOWs are applied simultaneously to both inputs S and R
C. a LOW is applied to the S input while a HIGH is applied to the R input
D. a HIGH is applied to the S input while a LOW is applied to the R input

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Question 20

What is the significance of the J and K terminals on the J-K flip-flop?

A. There is no known significance in their designations.
B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
D. All of the other letters of the alphabet are already in use.

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Question 21

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

A. An invalid state will exist.
B. No change will occur in the output.
C. The output will toggle.
D. The output will reset.

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Question 22

How is a J-K flip-flop made to toggle?

A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1

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Question 23

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

A. 1 kHz
B. 2 kHz
C. 4 kHz
D. 16 kHz

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Question 24

In VHDL, how many inputs will a primitive JK flip-flop have?

A. 2
B. 3
C. 4
D. 5

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Question 25

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

A. the clock pulse is LOW
B. the clock pulse is HIGH
C. the clock pulse transitions from LOW to HIGH
D. the clock pulse transitions from HIGH to LOW

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Question 26

The pulse width of a one-shot circuit is determined by ________.

A. a resistor and capacitor
B. two resistors
C. two capacitors
D. none of the above

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Question 27

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1

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Question 28

What is another name for a one-shot?

A. Monostable
B. Multivibrator
C. Bistable
D. Astable

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Question 29

Propagation delay time, tPLH, is measured from the ________.

A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C. preset input to the LOW-to-HIGH transition of the output
D. clear input to the HIGH-to-LOW transition of the output

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Question 30

What is the hold condition of a flip-flop?

A. both S and R inputs activated
B. no active S or R input
C. only S is active
D. only R is active

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Question 31

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

A. SET
B. RESET
C. clear
D. invalid

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Question 32

One example of the use of an S-R flip-flop is as a(n):

A. racer
B. astable oscillator
C. binary storage register
D. transition pulse generator

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Question 33

In VHDL, in which declaration section is a COMPONENT declared?

A. Architecture
B. Library
C. Entity
D. Port map

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Question 34

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

A. 0
B. 11
C. 1
D. 10

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Question 35

The timing network that sets the output frequency of a 555 astable circuit contains ________.

A. three external resistors are used
B. two external resistors and an external capacitor are used
C. an external resistor and two external capacitors are used
D. no external resistor or capacitor is required

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Question 36

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A. very long.
B. very short.
C. at a maximum value to enable the input control signals to stabilize.
D. of no consequence as long as the levels are within the determinate range of value.

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Question 37

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

A. parity error checking
B. ones catching
C. digital discrimination
D. digital filtering

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Question 38

To completely load and then unload an 8-bit register requires how many clock pulses?

A. 2
B. 4
C. 8
D. 16

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Question 39

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A. cross coupling
B. gate impedance
C. low input voltages
D. asynchronous operation

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Question 40

A J-K flip-flop is in a "no change" condition when ________.

A. J = 1, K = 1
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 0, K = 0

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Question 41

What is one disadvantage of an S-R flip-flop?

A. It has no enable input.
B. It has an invalid state.
C. It has no clock input.
D. It has only a single output.

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Question 42

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

A. clock is LOW
B. slave is transferring
C. flip-flop is reset
D. clock is HIGH

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Question 43

A positive edge-triggered D flip-flop will store a 1 when ________.

A. the D input is HIGH and the clock transitions from HIGH to LOW
B. the D input is HIGH and the clock transitions from LOW to HIGH
C. the D input is HIGH and the clock is LOW
D. the D input is HIGH and the clock is HIGH

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Question 44

How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

A. It can't be done.
B. Invert the Q outputs.
C. Invert the S-R inputs.

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Question 45

When is a flip-flop said to be transparent?

A. when the Q output is opposite the input
B. when the Q output follows the input
C. when you can see through the IC packaging

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Question 46

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

A. TRUE
B. FALSE

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Question 47

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

A. TRUE
B. FALSE

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Question 48

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

A. No change will occur in the output.
B. An invalid state will exist.
C. The output will toggle.
D. The output will reset.

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Question 49

Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.

A. TRUE
B. FALSE

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Question 50

How many flip-flops are in the 7475 IC?

A. 1
B. 2
C. 4
D. 8

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Question 51

On a J-K flip-flop, when is the flip-flop in a hold condition?

A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1

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Question 52

Which of the following is correct for a D latch?

A. The output toggles if one of the inputs is held HIGH.
B. Q output follows the input D when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D. The output complement follows the input when enabled.

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Question 53

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz

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Question 54

For an S-R flip-flop to be set or reset, the respective input must be:

A. installed with steering diodes
B. in parallel with a limiting resistor
C. LOW
D. HIGH

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Question 55

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

A. The power supply is probably noisy.
B. The switch contacts are bouncing.
C. The socket contacts on the register IC are corroded.
D. The register IC is intermittent and failure is imminent.

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Question 56

Which of the following is correct for a gated D flip-flop?

A. The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D. Q output follows the input D when the enable is HIGH.

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Question 57

Which of the following is not generally associated with flip-flops?

A. Hold time
B. Propagation delay time
C. Interval time
D. Set up time

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Question 58

What is the difference between the enable input of the 7475 and the clock input of the 7474?

A. The 7475 is edge-triggered.
B. The 7474 is edge-triggered.

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Question 59

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A. The logic level at the D input is transferred to Q on NGT of CLK.
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. The Q output is ALWAYS identical to the D input when CLK = PGT.
D. The Q output is ALWAYS identical to the D input.

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Question 60

Why are the S and R inputs of a gated flip-flop said to be synchronous?

A. They must occur with the gate.
B. They occur independent of the gate.

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