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Integrated-Circuit Logic Families MCQ Questions & Answers

Integrated-Circuit Logic Families MCQs : This section focuses on the "Integrated-Circuit Logic Families". These Multiple Choice Questions (MCQs) should be practiced to improve the Integrated-Circuit Logic Families skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.

Question 1

A "floating" TTL input may be defined as:

A. unused input that is tied to Vcc through a 1 k resistor.
B. unused input that is tied to used inputs.
C. unused input that is tied to the ground.
D. unused input that is not connected.

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Question 2

A logic signal experiences a delay in going through a circuit. The two propagation delay times are defined as:

A. tPLH and tPHL.
B. tDLH and tDHL.
C. tHPL and tlph.
D. tLDH and tHDL.

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Question 3

Generally, the voltage measured at an unused TTL input would typically be measured between:

A. 1.4 to 1.8 V.
B. 0 to 5 V.
C. 0 to 1.8 V.
D. 0.8 to 5 V.

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Question 4

Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:

A. a greater current/voltage capability than an ordinary logic circuit.
B. greater input current/voltage capability than an ordinary logic circuit.
C. a smaller output current/voltage capability than an ordinary logic.
D. greater input and output current/voltage capability than an ordinary logic circuit.

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Question 5

The bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:

A. emitter-coupled logic (ECL).
B. current-mode logic (CML).
C. transistor-transistor logic (TTL).
D. emitter-coupled logic (ECL) and transistor-transistor logic (TTL).

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Question 6

The IEEE/ANSI notation of an internal underlined diamond denotes:

A. totem-pole outputs.
B. open-collector outputs.
C. quadrature amplifiers.
D. tristate buffers.

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Question 7

What are the major differences between the 5400 and 7400 series of ICs?

A. The 5400 series are military grade and require tighter supply voltages and temperatures.
B. The 5400 series are military grade and allow for a wider range of supply voltages and temperatures.
C. The 7400 series are an improvement over the original 5400s.
D. The 7400 series was originally developed by Texas Instruments. The 5400 series was brought out by National Semiconductors after TI's patents expired, as a second supply source.

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Question 8

What causes low-power Schottky TTL to use less power than the 74XX series TTL?

A. The Schottky-clamped transistor
B. Nothing. The 74XX series uses less power.
C. A larger value resistor
D. Using NAND gates

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Question 9

What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)?

A. 5
B. 10
C. 50
D. 100

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Question 10

What is the static charge that can be stored by your body as you walk across a carpet?

A. 300 volts
B. 3,000 volts
C. 30,000 volts
D. Over 30,000 volts

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Question 11

What is unique about TTL devices such as the 74S00?

A. The gate transistors are silicon (S), and the gates therefore have lower values of leakage current.
B. The S denotes the fact that a single gate is present in the IC rather than the usual package of 2–6 gates.
C. The S denotes a slow version of the device, which is a consequence of its higher power rating.
D. The devices use Schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation.

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Question 12

What must be done to interface CMOS to TTL?

A. A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.
B. As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
C. A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates.
D. The two series cannot be interfaced without the use of special interface buffers designed for that purpose, such as the open-collector buffers.

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Question 13

Whenever a totem-pole TTL output goes from LOW to HIGH, a high-amplitude current spike is drawn from the Vcc supply. How is this effect corrected to a digital circuit?

A. By connecting a radio-frequency capacitor from Vcc to ground.
B. By using a switching power supply
C. By connecting a capacitor from Vout to ground
D. By connecting a large resistor from Vcc to Vout

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Question 14

Which of the following logic families has the highest maximum clock frequency?


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Question 15

Which of the following logic families has the highest noise margin?


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Question 16

Which of the following logic families has the shortest propagation delay?


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Question 17

Which of the following statements apply to CMOS devices?

A. The devices should not be inserted into circuits with the power on.
B. All tools, test equipment, and metal workbenches should be tied to earth ground.
C. The devices should be stored and shipped in antistatic tubes or conductive foam.
D. All of the above.

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Question 18

Which of the following summarizes the important features of ECL?

A. Low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption
B. Good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time
C. Slow propagation time, high frequency response, low power consumption, and high output voltage swings
D. Poor noise immunity, positive supply voltage operation, good low frequency operation, and low power

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Question 19

Which of the following will not normally be found on a data sheet?

A. Minimum HIGH level output voltage
B. Maximum LOW level output voltage
C. Minimum LOW level output voltage
D. Maximum HIGH level input current

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Question 20

Which of the logic families listed below allows the highest operating frequency?

A. 74AS
D. 54S

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Question 21

Why is the fan-out of CMOS gates frequency dependent?

A. Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
B. When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
C. The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
D. The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.

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