Integrated Circuit Technologies MCQs : This section focuses on the "Integrated Circuit Technologies". These Multiple Choice Questions (MCQs) should be practiced to improve the Integrated Circuit Technologies skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
For a CMOS gate, which is the best speed-power product?
A. 1.4 pJ
B. 1.6 pJ
C. 2.4 pJ
D. 3.3 pJ
TTL is alive and well, particularly in ________.
A. industrial applications
B. educational applications
C. military applications
D. commercial applications
Which equation is correct?
A. VNL = VIL(max) + VOL(max)
B. VNH = VOH(min) + VIH(min)
C. VNL = VOH(min) – VIH(min)
D. VNH = VOH(min) – VIH(min)
An open-collector output requires ________.
A. a pull-down resistor
B. a pull-up resistor
C. no output resistor
D. an output resistor
Which is not a precaution for handling CMOS?
A. Devices should be placed with pins down on a grounded surface, such as a metal plate.
B. All tools, test equipment, and metal workbenches should be earth grounded.
C. CMOS devices should not be inserted into sockets or PC boards with the power on.
D. Wear wool clothes at all times.
The greater the propagation delay, the ________.
A. lower the maximum frequency
B. higher the maximum frequency
C. maximum frequency is unaffected
D. minimum frequency is unaffected
A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)), ________.
A. 16 mA
B. 20 mA
C. 16 A
D. 20 A
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________.
A. 5.5 mW
B. 5.5 W
C. 5 mW
D. 1.1 mW
Which transistor element is used in CMOS logic?
Which is not an output state for tristate logic?
Which factor does not affect CMOS loading?
A. Charging time associated with the output resistance of the driving gate
B. Discharging time associated with the output resistance of the driving gate
C. Output capacitance of the load gates
D. Input capacitance of the load gates
The nominal value of the dc supply voltage for TTL and CMOS is ________.
A. +3 V
B. +5 V
C. +9 V
D. +12 V
In a TTL circuit, if an excessive number of load gate inputs are connected, ________.
A. VOH(min) drops below VOH
B. VOH drops below VOH(min)
C. VOH exceeds VOH(min)
D. VOH and VOH(min) are unaffected
The active switching element used in all TTL circuits is the ________.
A. bipolar junction transistor (BJT)
B. field-effect transistor (FET)
C. metal-oxide semiconductor field-effect transistor (MOSFET)
D. unijunction transistor (UJ)
Which is not part of emitter-coupled logic (ECL)?
A. Differential amplifier
B. Bias circuit
C. Emitter-follower circuit
D. Totem-pole circuit
PMOS and NMOS circuits are used largely in ________.
A. MSI functions
B. LSI functions
C. diode functions
D. TTL functions
An open-drain gate is the CMOS counterpart of ________.
A. an open-collector TTL gate
B. a tristate TTL gate
C. a bipolar junction transistor
D. an emitter-coupled logic gate
A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?
A. –12.8 mA
B. –8 mA
C. –1.6 mA
D. –25.6 mA
Which logic family combines the advantages of CMOS and TTL?
One output structure of a TTL gate is often referred to as a ________.
A. totem-pole arrangement
B. diode arrangement
C. JBT arrangement
D. base, emitter, collector arrangement
Most TTL logic used today is some form of ________.
A. Schottky TTL
B. tristate TTL
C. low-power TTL
D. open-collector TTL
Which is not a MOSFET terminal?
It is best not to leave unused TTL inputs unconnected (open) because of TTL's ________.
A. noise sensitivity
B. low-current requirement
C. open-collector outputs
D. tristate construction