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Interconnection Topologies MCQ Questions & Answers

Interconnection Topologies MCQs : This section focuses on the "Interconnection Topologies". These Multiple Choice Questions (MCQs) should be practiced to improve the Interconnection Topologies skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.




Question 1

Bus switches are present in

A. bus window technique
B. crossbar switching
C. linked input/output
D. shared bus

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Question 2

In multiport memory configuration, the processor(s) that address the multiport memory is(are)

A. 1
B. 2
C. 3
D. many

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Question 3

In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is

A. one processor
B. two processors
C. more than two processors
D. none of the mentioned

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Question 4

The array processor architecture is an example of

A. star
B. loop
C. complete
D. regular

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Question 5

The configuration that is not suitable for a large number of processors is

A. star
B. loop
C. complete
D. regular

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Question 6

The configuration, in which all the processing elements are connected to a central switching element, that may be independent processor via dedicated paths is

A. star
B. loop
C. complete
D. irregular

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Question 7

The disadvantage of the bus window technique is

A. both processors must know about bus window
B. both processors must know the address map
C. loss of effective local memory space
D. all of the mentioned

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Question 8

The memory of a microprocessor serves as

A. storage of individual instructions
B. temporary storage for the data
C. storing common instructions or data for all processors
D. all of the mentioned

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Question 9

The memory space of a processor that is mapped to other processor/processors and vice-versa is known as

A. multi microprocessor system
B. memory technique
C. bus window technique
D. mapping technique

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Question 10

Which of the following is not a type of configuration that is based on physical interconnections between the processors?

A. star configuration
B. loop configuration
C. regular topologies
D. incomplete interconnection

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