Memory and Storage MCQs : This section focuses on the "Memory and Storage". These Multiple Choice Questions (MCQs) should be practiced to improve the Memory and Storage skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
A 64-bit word consists of ________.
A. 4 bytes
B. 8 bytes
C. 10 bytes
D. 12 bytes
A 64-Mbyte SIMM is installed into a system, but when a memory test is executed, the SIMM is detected as a 32-Mbyte device. What is a possible cause?
A. The memory module was not installed properly.
B. The voltage on the memory module is incorrect.
C. The most significant address line is stuck high or low.
D. The address decoder on the SIMM is faulty.
A CD-R disk is created by applying heat to special chemicals on the disk and these chemicals reflect less light than the areas that are not burned, thus creating the same effect as a pit does on a regular CD.
A major disadvantage of the mask ROM is that it:
A. is time consuming to change the stored data when system requirements change
B. is very expensive to change the stored data when system requirements change
C. cannot be reprogrammed if stored data needs to be changed
D. has an extremely short life expectancy and requires frequent replacement
Address decoding for dynamic memory chip control may also be used for:
A. controlling refresh circuits
B. read and write control
C. chip selection and address location
D. memory mapping
Advantage(s) of an EEPROM over an EPROM is/are:
A. the EPROM can be erased with ultraviolet light in much less time than an EEPROM
B. the EEPROM can be erased and reprogrammed without removal from the circuit
C. the EEPROM has the ability to erase and reprogram individual words
D. the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words
An 8-bit address code can select ________.
A. 8 locations in memory
B. 256 locations in memory
C. 65,536 locations in memory
D. 131,072 locations in memory
CCD stands for ________.
A. capacitor charging device
B. capacitor-capacitor drain
C. charged-capacitor device
D. charge-coupled device
Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.
Describe the timing diagram of a write operation.
A. First the data is set on the data bus and the address is set, then the write pulse stores the data.
B. First the address is set, then the data is set on the data bus, and finally the read pulse stores the data.
C. First the write pulse stores the data, then the address is set, and finally the data is set on the data bus.
D. First the data is set on the data bus, then the write pulse stores the data, and finally the address is set.
Dynamic memory cells store a data bit in a ________.
EEPROM stands for ________.
A. encapsulated electrical programmable read-only memory
B. elementary electrical programmable read-only memory
C. electrically erasable programmable read-only memory
D. elementary erasable programmable read-only memory
Eight bits of digital data are normally referred to as a:
FIFO is formed by an arrangement of ________.
C. MOS cells
D. shift registers
How can UV erasable PROMs be recognized?
A. There is a small window on the chip.
B. They will have a small violet dot next to the #1 pin.
C. Their part number always starts with a "U", such as in U12.
D. They are not readily identifiable, since they must always be kept under a small cover.
How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?
How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?
How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM?
How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?
How many address lines would be required for a 2K × 4 memory chip?
How many storage locations are available when a memory device has 12 address lines?
In a DRAM, what is the state of R/W during a read operation?
D. None of the above
In general, the ________ have the smallest bit size and the ________ have the largest.
A. EEPROMs, Flash
B. SRAM, mask ROM
C. mask ROM, SRAM
D. DRAM, PROM
L1 is known as ________.
A. primary cache
B. secondary cache
Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________.
On a CD-ROM, ________ are raised areas representing a 1.
On a CD-ROM, ________ are recessed areas representing a 0.
One of the most important specifications on magnetic media is the ________.
A. rotation speed
B. tracks per inch
C. data transfer rate
D. polarity reversal rate
ROMs retain data when the ________.
A. power is off
B. power is on
C. system is down
D. all of the above
Select the statement that best describes Read-Only Memory (ROM).
A. nonvolatile, used to store information that changes during system operation
B. nonvolatile, used to store information that does not change during system operation
C. volatile, used to store information that changes during system operation
D. volatile, used to store information that does not change during system operation
Select the statement that best describes the fusible-link PROM.
A. user-programmable, one-time programmable
B. manufacturer-programmable, one-time programmable
C. user-programmable, reprogrammable
D. manufacturer-programmable, reprogrammable
Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?
The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________.
The check sum method of testing a ROM:
A. indicates if the data in more than one memory location is incorrect.
B. provides a means for locating and correcting data errors in specific memory locations.
C. allows data errors to be pinpointed to a specific memory location.
D. simply indicates that the contents of the ROM are incorrect.
The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.
A. address decoding
B. bus contention
C. bus collisions
D. address multiplexing
The ideal memory ________.
A. has high storage capacity
B. is nonvolatile
C. has in-system read and write capacity
D. has all of the above characteristics
The location of a unit of data in a memory array is called its ________.
The main advantage of semiconductor RAM is its ability to:
A. retain stored data when power is interrupted or turned off
B. be written to and read from rapidly
C. be randomly accessed
D. be sequentially accessed
The mask ROM is ________.
A. permanently programmed during the manufacturing process
C. easy to reprogram
D. extremely expensive
The mask ROM is ________.
A. MOS technology
B. diode technology
C. resistor-diode technology
D. DROM technology
The periodic recharging of DRAM memory cells is called ________.
The reason the data outputs of most ROM ICs are tristate outputs is to:
A. allow for three separate data input lines.
B. allow the bidirectional flow of data between the bus lines and the ROM registers.
C. permit the connection of many ROM chips to a common data bus.
D. isolate the registers from the data bus during read operations.
The refresh period for capacitors used in DRAMs is ________.
A. 2 ms
B. 2 s
C. 64 ms
D. 64 s
The smallest unit of binary data is the ________.
The storage element for a static RAM is the ________.
The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:
A. access time
B. data hold
C. read cycle time
D. write enable time
To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?
A. The address input
B. The output enable
C. The chip enable
D. The data input
Typically, how often is DRAM refreshed?
A. 2 to 8 ms
B. 4 to 16 ms
C. 8 to 16 s
D. 1 to 2 s
What are the typical values of tOE?
A. 10 to 20 ns for bipolar
B. 25 to 100 ns for NMOS
C. 12 to 50 ns for CMOS
D. All of the above
What does the term "random access" mean in terms of memory?
A. Addresses must be accessed in a specific order.
B. Any address can be accessed in any order.
What is a major disadvantage of RAM?
A. Its access speed is too slow.
B. Its matrix size is too big.
C. It is volatile.
D. High power consumption
What is a multitap digital delay line?
A. a series of inverter gates with RC circuits between each one
B. a series of inverter gates with RL circuits between each one
C. a series of NAND gates with RC circuits between each one
D. a series of NAND gates with RL circuits between each one
What is the bit storage capacity of a ROM with a 1024 × 8 organization?
What is the computer main memory?
A. Hard drive and RAM
B. CD-ROM and hard drive
C. RAM and ROM
D. CMOS and hard drive
What is the difference between static RAM and dynamic RAM?
A. Static RAM must be refreshed, dynamic RAM does not.
B. There is no difference.
C. Dynamic RAM must be refreshed, static RAM does not.
What is the maximum time required before a dynamic RAM must be refreshed?
A. 2 ms
B. 4 ms
C. 8 ms
D. 10 ms
What is the principal advantage of using address multiplexing with DRAM memory?
A. reduced memory access time
B. reduced requirement for constant refreshing of the memory contents
C. reduced pin count and decrease in package size
D. It eliminates the requirement for a chip-select input line, thereby reducing the pin count.
What part of a Flash memory architecture manages all chip functions?
A. I/O pins
B. floating-gate MOSFET
C. command code
D. program verify code
What two functions does a DRAM controller perform?
A. address multiplexing and data selection
B. address multiplexing and the refresh operation
C. data selection and the refresh operation
D. data selection and CPU accessing
When a RAM module passes the checkerboard test it is:
A. able to read and write only 1s.
C. probably good.
D. able to read and write only 0s.
Which is not a hard disk performance parameter?
A. Seek time
B. Break time
C. Latency period
D. Access time
Which is not a magnetic storage device?
A. Magnetic disk
B. Magnetic tape
C. Magneto-optical disk
D. Optical disk
Which is not a removable drive?
Which is not part of a hard disk drive?
C. Read/write head
Which is/are the basic refresh mode(s) for dynamic RAM?
A. Burst refresh
B. Distributed refresh
C. Open refresh
D. Burst refresh and distributed refresh
Which of the following best describes EPROMs?
A. EPROMs can be programmed only once.
B. EPROMs can be erased by UV.
C. EPROMs can be erased by shorting all inputs to the ground.
D. All of the above.
Which of the following best describes random-access memory (RAM)?
A. a type of memory in which access time depends on memory location
B. a type of memory that can be written to only once but can be read from an infinite number of times
C. a type of memory in which access time is the same for each memory location
D. mass memory
Which of the following best describes static memory devices?
A. memory devices that are magnetic in nature and do not require constant refreshing
B. memory devices that are magnetic in nature and require constant refreshing
C. semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed
D. semiconductor memory devices in which stored data is retained as long as power is applied
Which of the following best describes volatile memory?
A. memory that retains stored information when electrical power is removed
B. memory that loses stored information when electrical power is removed
C. magnetic memory
Which of the following describes the action of storing a bit of data in a mask ROM?
A. A 1 is stored in a bipolar cell by opening the base connection to the address line.
B. A 0 is stored in a bipolar cell by shorting the base connection to the address line.
C. A 1 is stored by connecting the gate of a MOS cell to the address line.
D. A 0 is stored by connecting the gate of a MOS cell to the address line.
Which of the following faults will the checkerboard pattern test for in RAM?
A. Short between adjacent cells
B. Ability to store both 0s and 1s
C. Dynamically introduced errors between cells
D. All of the above
Which of the following is normally used to initialize a computer system's hardware?
A. Bootstrap memory
B. Volatile memory
C. External mass memory
D. Static memory
Which of the following is not a flash memory mode or operation?
Which of the following is NOT a type of memory?
Which of the following is one of the basic characteristics of DRAMs?
A. DRAMs must have a constantly changing input.
B. DRAMs must be periodically refreshed in order to be able to retain data.
C. DRAMs have a broader "dynamic" storage range than other types of memories.
D. DRAMs are simpler devices than other types of memories.
Which of the following memories is volatile?
Which of the following memories uses a MOS capacitor as its memory cell?
Which of the following RAM timing parameters determine its operating speed?
B. tAA and tACS
C. tCO and tOD
D. tRC and tWC
Which type of ROM can be erased by an electrical signal?
B. mask ROM
Which type of ROM can be erased by UV light?
B. mask ROM
Which type of ROM has to be custom built by the factory?
B. mask ROM
Why are ROMs called nonvolatile memory?
A. They lose memory when power is removed.
B. They do not lose memory when power is removed.
Why do most dynamic RAMs use a multiplexed address bus?
A. It is the only way to do it.
B. to make it faster
C. to keep the number of pins on the chip to a minimum
Why is a refresh cycle necessary for a dynamic RAM?
A. to clear the flip-flops
B. to set the flip-flops
C. The refresh cycle discharges the capacitor cells.
D. The refresh cycle keeps the charge on the capacitor cells.