Pentium 4 Features MCQs : This section focuses on the "Pentium 4 Features". These Multiple Choice Questions (MCQs) should be practiced to improve the Pentium 4 Features skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
After the micro-ops are issued by the microcode ROM, the control goes to
A. trace cache
B. front end branch predictor
C. execution module
D. instruction decoder
Question 2
Each logical processor has
A. one 64-byte streaming buffer
B. one 32-byte streaming buffer
C. two 64-byte streaming buffers
D. two 32-byte streaming buffers
Question 3
If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
A. microcode ROM
B. front end branch predictor
C. execution module
D. instruction decoder
Question 4
If the logical processors want to execute complex IA-32 instructions simultaneously then the number of microcode instruction pointers required is
A. 1
B. 2
C. 3
D. 4
Question 5
If there is a trace cache miss, then the instruction bytes are required to be fetched from the
A. instruction decoder
B. Level2 cache
C. execution module
D. none of the mentioned
Question 6
In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to
A. trace cache
B. front end branch predictor
C. microcode ROM
D. none
Question 7
The advantage of static prediction is
A. simple and fast
B. does not require table lookups or calculations
C. performs without much degradation
D. all of the mentioned
Question 8
The BHT keeps a record that indicates the likelihood of the branches grouped as
A. strongly taken
B. taken
C. not taken
D. all of the mentioned
Question 9
The dynamic branch prediction algorithms use
A. Branch History Table (BHT)
B. Branch Target Buffer (BTB)
C. Branch History Table and Branch Target Buffer
D. None
Question 10
The feature of Pentium 4 is
A. works based on NetBurst microarchitecture
B. clock speed ranges from 1.4GHz to 1.7GHz
C. has hyper-pipelined technology
D. all of the mentioned
Question 11
The front module of Pentium 4 consists of
A. trace cache
B. microcode ROM
C. front end branch predictor
D. all of the mentioned
Question 12
The Instruction Translation Lookaside Buffer(ITLB) is present in
A. trace cache
B. instruction decoder
C. logical processors
D. all of the mentioned
Question 13
The prediction that is based on a statistical assumption that the majority of backward branches occur in repetitive loops is
A. static prediction
B. dynamic prediction
C. branch prediction
D. none
Question 14
The unit that decodes the instructions concurrently and translate them into micro-operations is
A. trace cache
B. instruction decoder
C. execution module
D. front end branch predictor
Question 15
The unit that predicts the locations from where the next instruction bytes are fetched is
A. trace cache
B. front end branch predictor
C. execution module
D. instruction decoder
Question 16
The unit that preserves the history of each conditional branch is
A. Branch Target Buffer (BTB)
B. Branch History Table (BHT)
C. Static prediction
D. Dynamic prediction
Question 17
Trace cache can store the micro-ops upto a range of
A. 6 K decoded micro-ops
B. 8 K decoded micro-ops
C. 10 K decoded micro-ops
D. 12 K decoded micro-ops
Question 18
Which of the following is not a module of Pentium 4 architecture?
A. front end module
B. execution module
C. control module
D. none
Question 19
Which of the following is a type of branch prediction?
A. static prediction
B. dynamic prediction
C. static and dynamic prediction
D. none