Pentium-Pro & Pentium2 MCQs : This section focuses on the "Pentium-Pro & Pentium2". These Multiple Choice Questions (MCQs) should be practiced to improve the Pentium-Pro & Pentium2 skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
A dual independent bus has
A. Enhanced system bandwidth
B. CPU that can access both cache and memory simultaneously
C. High throughput
D. All of the mentioned
Question 2
Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
A. 1
B. 2
C. 3
D. 4
Question 3
In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
A. 1
B. 2
C. 3
D. 4
Question 4
During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
A. control unit
B. bus interface unit
C. execution unit
D. cpu
Question 5
The decoder unit in fetch-decode unit converts the instructions into
A. executable statements
B. machine language statements
C. MMX instructions
D. micro operations
Question 6
The execution in which the consecutive instruction execution in a sequential flow is hampered is
A. speculative execution
B. out of turn execution
C. dual independent bus
D. multiple branch prediction
Question 7
The feature of Pentium II is
A. high cache
B. operates at 2.8 volts
C. supports intel’s MMX instructions
D. all of the mentioned
Question 8
The logical source(s) and logical destination(s) that the micro operation has respectively are
A. 2,2
B. 1,3
C. 3,1
D. 3,2
Question 9
The microoperations that are converted by decoder are directly transferred to
A. decoder register
B. dispatch-execute unit
C. retire unit
D. register alias table
Question 10
The pool of instructions that are fetched is stored in an addressable memory called
A. tristate buffer
B. branch target buffer
C. reorder buffer
D. order buffer
Question 11
The instructions that pass through the fetch, decode and execution stages sequentially is known as
A. sequential instruction
B. sequence of fetch, decode and execution
C. linear instruction sequencing
D. non-linear instruction sequencing
Question 12
The results of speculative instruction execution is stored in
A. visible CPU registers
B. permanent memory
C. temporary memory
D. none
Question 13
The speed of Pentium-Pro when compared to that of Pentium is
A. equal
B. twice
C. thrice
D. two-third
Question 14
The unit that accepts the sequence of instructions from the instruction cache as input is
A. fetch-decode unit
B. dispatch-execute unit
C. retire unit
D. none
Question 15
The unit that is used to implement the multiple branch prediction in Pentium-Pro is
A. control unit
B. bus interface unit
C. branch target buffer
D. branch instruction register
Question 16
The unit that performs scheduling of instructions by determining the data dependencies is
A. fetch-decode unit
B. dispatch-execute unit
C. retire unit
D. none
Question 17
Which of the following is not an independent engine of Pentium-Pro?
A. fetch-decode unit
B. dispatch-execute unit
C. control-execute unit
D. retire unit
Question 18
Which of the following is not supported by Pentium-Pro?
A. multiple branch prediction
B. mmx instruction set
C. speculative execution
D. none