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Programmable Logic Device MCQ Questions & Answers

Programmable Logic Device MCQs : This section focuses on the "Programmable Logic Device". These Multiple Choice Questions (MCQs) should be practiced to improve the Programmable Logic Device skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.

Question 1

________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates.

A. Simplified AND gates
B. Fuses
C. Buffers
D. Latches

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Question 2

A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.

A. output logic macrocell
B. look-up table
C. parallel logic expander
D. logic element

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Question 3

A GAL is essentially a ________.

A. non-reprogrammable PAL
B. PAL that is programmed only by the manufacturer
C. very large PAL
D. reprogrammable PAL

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Question 4

A look-up table is simply a truth table with all the possible output connections listed with their desired input response.


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Question 5

A macrocell basically contains ________.

A. a programmable AND-OR gate array and some input buffers
B. an OR-gate array and some output logic
C. an AND-OR gate array and some output logic
D. licensed programming

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Question 6

A PAL16L8 has:

A. 10 inputs and 8 outputs.
B. 8 inputs and 8 outputs.
C. 16 inputs and 16 outputs.
D. 16 inputs and 8 outputs.

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Question 7

A slice consists of ________.

A. only two logic cells
B. between 2 and 8 logic cells
C. up to 16 logic cells
D. a single CLB

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Question 8

A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP.


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Question 9

A(n) ________ is a section of embedded logic that is commonly found in FPGAs.

B. core

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Question 10

ALM is the acronym for ________.

A. Array Logic Matrix
B. Arithmetic Logic Module
C. Asynchronous Local Modulator
D. Adaptive Logic Module

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Question 11

An SPLD listed as 16H8 would have ________.

A. active-HIGH outputs
B. active-LOW outputs
C. variable-level outputs
D. latches at the outputs

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Question 12

An SPLD listed as 22V10 has ________.

A. 10 inputs, 10 outputs, and requires a 22 V power source
B. 11 inputs, 11 outputs, and requires a 10 V power source
C. 22 inputs and 10 outputs
D. 10 inputs and 22 outputs

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Question 13

ASIC stands for:

A. advanced speed integrated circuit.
B. advanced standard integrated circuit.
C. application specific integrated circuit.
D. application speedy integrated circuit.

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Question 14

By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.


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Question 15

Cascade chains are closely associated with ________.

B. SOP functions
C. logic expansion
D. all of the above

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Question 16

CLB is the acronym for ________.

A. Configurable Logic Block
B. Configurable Logic Buffer
C. Critical Logic Buffer
D. Constant Logic Buffer

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Question 17

Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:

A. the polarity fuse is restored
B. sent to an inverter for output
C. sent immediately to an output pin
D. passed to the AND function for output

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Question 18

Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________.

A. DRAM, nonvolatile
B. SRAM, nonvolatile
C. SRAM, volatile
D. RAM, volatile

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Question 19

FPGA is the acronym for ________.

A. Flexible Programming [of] Generic Assemblies
B. Field Programmable Generic Array
C. Field Programmable Gate Array
D. Field Programmer's Gate Assembly

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Question 20

FPLA is:

A. a nonmemory programmable device.
B. a programmable AND array.
C. a programmable OR array.
D. All of the above

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Question 21

GAL is an acronym for ________.

A. Generic Array Logic
B. General Array Logic
C. Giant Array Logic
D. Generic Analysis Logic

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Question 22

How many combinations are handled in an LUT?

A. 4
B. 8
C. 16
D. 32

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Question 23

How many macrocells are in a MAX700S LAB?

A. 8
B. 16
C. 32
D. 64

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Question 24

How many pins are in an EDF10K70 package?

A. 70
B. 140
C. 240
D. 532

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Question 25

How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB?

A. 0
B. 5
C. 10
D. 20

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Question 26

In a FLEX10K, what two outputs will the LE produce?

A. The LAB and the fast track
B. ON and OFF
C. Hi-Z and ON
D. Hi-Z and OFF

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Question 27

In an OLMC, where does the FMUX signal go?

B. D flip-flop
C. Matrix

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Question 28

Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs.

A. 4,16
B. 8,16
C. 4,12
D. 6,12

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Question 29

MPGA stands for:

A. mass produced gated array.
B. Morgan-Phillips gated array.
C. memory programmed ROM.
D. mask programmed ROM.

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Question 30

Now many times can a GAL be erased and reprogrammed?

A. 0
B. At least 100
C. At least 1000
D. Over 10,000

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Question 31

PALs tend to execute ________ logic.


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Question 32

PIA is an acronym for ________.

A. Programmable Interface Array
B. Post Integrated Array
C. Programmable Input Array
D. Programmable Interconnect Array

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Question 33

Product terms are the outputs of which type of gate within a PLD array?

D. flip-flop

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Question 34

SPLDs, CPLDs, and FPGAs are all which type of device?


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Question 35

The Altera MAX 7000 series ________.

A. uses an E2PROM process technology
B. can have between 2 and 16 LABS and I/O control blocks
C. is available with DC supply voltages between 2.5 V and 5 V
D. all of the above

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Question 36

The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called:

A. macrocells
B. microcells
C. AND/OR arrays
D. fuse-link arrays

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Question 37

The complex programmable logic device (CPLD) features a(n) ________ type of memory.

A. volatile
B. nonvolatile
D. volitile EPROM

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Question 38

The difference between a PLA and a PAL is:

A. The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane.
B. The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane.
C. The PAL has more possible product terms than the PLA.
D. PALs and PLAs are the same thing.

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Question 39

The final step in the device programming sequence is ________.

A. compiling
B. downloading
C. simulation
D. synthesis

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Question 40

The GAL16V8 has:

A. 16 dedicated inputs.
B. 8 special function pins.
C. 8 pins that are used as inputs or outputs.
D. All of the above

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Question 41

The macrocells in a PAL/GAL are located ________.

A. after the programmable AND arrays
B. ahead of the programmable AND arrays
C. at the input terminals
D. at the output terminals

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Question 42

What can the GAL22V10 do that the GAL16V8 cannot?

A. It has an extra-large array.
B. It is in-system programmable.
C. It has twice the special function pins.
D. All of the above

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Question 43

What does a dot mean when placed on a PLD circuit diagram?

A. A point that is programmable
B. A point that cannot change
C. An intersection of logic blocks
D. An input or output point

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Question 44

What does the Altera FLEX10K PLD use in place of AND and OR arrays?

A. Nothing, it uses AND and OR arrays.
B. Look-up tables
C. SRAM-based memory
D. HPLD architecture

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Question 45

What gives a GAL its flexibility?

A. Its speed
B. Its reprogrammable EPROM
C. Its large logic arrays
D. Its programmable OLMCs

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Question 46

What is an EPM7128S?

A. An Altera MAX7000S CPLD
B. An Altera UP2
C. A DeVry eSOC

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Question 47

What is an OTP device?

A. Optical transporting port
B. Octal transmitting pixel
C. Operational topical portable
D. One-time programmable

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Question 48

What is another name for digital circuitry called sequential logic?

A. logic macrocell
B. logic array
C. flip-flop memory circuitry
D. inverter

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Question 49

What is PROM?


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Question 50

What is the defining difference between microprocessor/DSP systems and other digital systems?

A. The digital system follows a programmed sequence of instructions that the designer specified.
B. The microprocessor follows a programmed sequence of instructions that the designer specified.
C. The digital system is faster.
D. The microprocessor/DSP is faster.

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Question 51

What is the input/output pin configuration of the GAL22V10?

A. 10 output pins and 12 input pins
B. 2 special-purpose pins
C. 8 pins that are either inputs or outputs
D. All of the above

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Question 52

What is the major downfall of microprocessor/DSP systems?

A. Speed—they are too fast
B. Speed—they are too slow
C. Too much flexibility
D. Not enough flexibility

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Question 53

What is the status of a tristate output buffer on a MAX7000S family device?

A. It is permanently enabled or disabled.
B. It is controlled by one of the two global output enable pins.
C. It is controlled by other inputs or functions generated by other macrocells.
D. All of the above

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Question 54

What programmable technology is used in FPGA devices?

C. Antifuse
D. All of the above

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Question 55

When did the first PLD appear?

A. More than 10 years ago
B. More than 20 years ago
C. More than 30 years ago
D. More than 40 years ago

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Question 56

Which is a major digital system category?

A. Standard logic devices
C. Microprocessor/DSP devices
D. All of the above

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Question 57

Which is a mode of operation of the GAL16V8?

A. Simple mode
B. Complex mode
C. Registered mode
D. All of the above

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Question 58

Which is not a part of a GAL16V8's OLMC?


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Question 59

Which is not a type of PLD?


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Question 60

Which of the following increases the number of product terms by borrowing unused product from other macrocells?

A. Shared expander
B. Parallel expander
C. Series expander
D. Slice expander

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Question 61

Which of the following is true?

A. Altera uses PAL architecture and Xilinx uses PLA architecture.
B. Altera uses PLA architecture and Xilinx uses PAL architecture.
C. Altera and Xilinx both use PAL architecture.
D. Altera and Xilinx both use PLA architecture.

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Question 62

Which of the following testing procedures has one or more external moving parts?

A. Bed-of-nails
B. Flying probe
D. Boundary scan

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Question 63

Which of the following testing procedures uses the JTAG IEEE standard?

A. Bed-of-nails
B. Flying probe
D. Boundary scan

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Question 64

Which one of the following is an embedded function of the Stratix II FPGA?

A. AND-OR logic
B. Programmable SOP
C. Digital signal processing
D. None of the above

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Question 65

Which type of PLD could be used to program basic logic functions?

D. all the above

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Question 66

Why have PLDs taken over so much of the market?

A. One PLD does the work of many ICs.
B. The PLDs are cheaper.
C. Less power is required.
D. All of the above

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