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Shift Registers MCQ Questions & Answers

Shift Registers MCQs : This section focuses on the "Shift Registers". These Multiple Choice Questions (MCQs) should be practiced to improve the Shift Registers skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.




Question 1

A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

A. right, one
B. right, two
C. left, one
D. left, three

View Answer

Question 2

A 74HC195 4-bit parallel access shift register can be used for ________.

A. serial in/serial out operation
B. serial in/parallel out operation
C. parallel in/serial out operation
D. all of the above

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Question 3

A modulus-12 ring counter requires a minimum of ________.

A. 10 flip-flops
B. 12 flip-flops
C. 6 flip-flops
D. 2 flip-flops

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Question 4

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A. ring shift
B. clock
C. Johnson
D. binary

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Question 5

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

A. 0
B. 1111
C. 111
D. 1000

View Answer

Question 6

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

A. 1.67 s
B. 26.67 s
C. 26.7 ms
D. 267 ms

View Answer

Question 7

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.

A. 16 s
B. 8 s
C. 4 s
D. 2 s

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Question 8

Another way to connect devices to a shared data bus is to use a ________.

A. circulating gate
B. transceiver
C. bidirectional encoder
D. strobed latch

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Question 9

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

A. 1100
B. 11
C. 0
D. 1111

View Answer

Question 10

By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.

A. parallel-in, serial, parallel
B. serial-in, parallel, serial
C. series-parallel-in, series, parallel
D. bidirectional in, parallel, series

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Question 11

Computers operate on data internally in a ________ format.

A. tristate
B. universal
C. parallel
D. serial

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Question 12

How can parallel data be taken out of a shift register simultaneously?

A. Use the Q output of the first FF.
B. Use the Q output of the last FF.
C. Tie all of the Q outputs together.
D. Use the Q output of each FF.

View Answer

Question 13

How is a strobe signal used when serially loading a shift register?

A. to turn the register on and off
B. to control the number of clocks
C. to determine which output Qs are used
D. to determine the FFs that will be used

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Question 14

How many clock pulses will be required to completely load serially a 5-bit shift register?

A. 2
B. 3
C. 4
D. 5

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Question 15

How much storage capacity does each stage in a shift register represent?

A. One bit
B. Two bits
C. Four bits (one nibble)
D. Eight bits (one byte)

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Question 16

How would a latch circuit be used in a microprocessor system?

A. as transportation for Intel employees
B. for a group of data that is the same
C. as a set of common connections for transfer of data

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Question 17

If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

A. 1101000000
B. 11010000
C. 1100000000
D. 0

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Question 18

If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

A. 11101011
B. 10111
C. 11110000
D. 0

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Question 19

In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A. 1
B. 2
C. 4
D. 8

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Question 20

In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A. 2
B. 6
C. 12
D. 24

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Question 21

In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

A. 1110
B. 1
C. 1100
D. 1000

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Question 22

On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.

A. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
B. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
C. Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1

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Question 23

On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.

A. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

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Question 24

Ring shift and Johnson counters are:

A. synchronous counters
B. aynchronous counters
C. true binary counters
D. synchronous and true binary counters

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Question 25

Stepper motors have become popular in digital automation systems because ________.

A. of their low cost
B. they are driven by sequential digital signals
C. they can be used to provide repetitive mechanical movement
D. they are driven by sequential digital signals and can be used to provide repetitive mechanical movement

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Question 26

The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

A. 0
B. 10
C. 1000
D. 1111

View Answer

Question 27

The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

A. 10011100
B. 11000000
C. 1100
D. 11110000

View Answer

Question 28

The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.

A. 10111000
B. 10110111
C. 11110000
D. 11111100

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Question 29

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

A. 1110
B. 1
C. 101
D. 110

View Answer

Question 30

The primary purpose of a three-state buffer is usually:

A. to provide isolation between the input device and the data bus
B. to provide the sink or source current required by any device connected to its output without loading down the output device
C. temporary data storage
D. to control data flow

View Answer

Question 31

To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.

A. divide-by-4 clock pulse
B. sequence generator
C. strobe line
D. multiplexer

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Question 32

To operate correctly, starting a ring shift counter requires:

A. clearing all the flip-flops
B. presetting one flip-flop and clearing all others
C. clearing one flip-flop and presetting all others
D. presetting all the flip-flops

View Answer

Question 33

To serially shift a nibble (four bits) of data into a shift register, there must be ________.

A. one clock pulse
B. four clock pulses
C. eight clock pulses
D. one clock pulse for each 1 in the data

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Question 34

What are the three output conditions of a three-state buffer?

A. HIGH, LOW, float
B. 1, 0, float
C. both of the above
D. neither of the above

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Question 35

What does the output enable do on the 74395A chip?

A. It determines when data can be loaded.
B. It forces all outputs to go HIGH.
C. It forces all outputs to go LOW.
D. It activates the three-state buffer.

View Answer

Question 36

What is a recirculating register?

A. serial out connected to serial in
B. all Q outputs connected together
C. a register that can be used over again

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Question 37

What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

A. tristate
B. end around
C. universal
D. conversion

View Answer

Question 38

What is a transceiver circuit?

A. a buffer that transfers data from input to output
B. a buffer that transfers data from output to input
C. a buffer that can operate in both directions

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Question 39

What is meant by parallel load of a shift register?

A. All FFs are preset with data.
B. Each FF is loaded with data, one at a time.

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Question 40

What is the difference between a ring shift counter and a Johnson shift counter?

A. There is no difference.
B. A ring is faster.
C. The feedback is reversed.
D. The Johnson is faster.

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Question 41

What is the difference between a shift-right register and a shift-left register?

A. There is no difference.
B. the direction of the shift

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Question 42

What is the function of a buffer circuit?

A. to provide an output that is inverted from that on the input
B. to provide an output that is equal to its input
C. to clean up the input
D. to clean up the output

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Question 43

What is the preset condition for a ring shift counter?

A. all FFs set to 1
B. all FFs cleared to 0
C. a single 0, the rest 1
D. a single 1, the rest 0

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Question 44

What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

A. parallel-in, parallel-out
B. parallel-in, serial-out
C. serial-in, parallel-out
D. serial-in, serial-out

View Answer

Question 45

When is it important to use a three-state buffer?

A. when two or more outputs are connected to the same input
B. when all outputs are normally HIGH
C. when all outputs are normally LOW
D. when two or more outputs are connected to two or more inputs

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Question 46

When the output of a tristate shift register is disabled, the output level is placed in a:

A. float state
B. LOW state
C. high-impedance state
D. float or high-impedance state

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Question 47

Which is not characteristic of a shift register?

A. Serial in/parallel in
B. Serial in/parallel out
C. Parallel in/serial out
D. Parallel in/parallel out

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Question 48

Which type of device may be used to interface a parallel data format with external equipment's serial format?

A. key matrix
B. UART
C. memory chip
D. series in, parallel out

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Question 49

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms

View Answer

Question 50

With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.

A. 12 s
B. 120 s
C. 12 ms
D. 120 ms

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Question 51

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________

A. 0
B. 1111
C. 111
D. 1000

View Answer

Question 52

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?

A. Tristate
B. End around
C. Universal
D. Conversion

View Answer

Question 53

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________

A. 16 us
B. 8 us
C. 4 us
D. 2 us

View Answer

Question 54

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

A. 1100
B. 11
C. 0
D. 1111

View Answer

Question 55

Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.

A. 2
B. 3
C. 4
D. 5

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Question 56

Clock divider slow down the input clock of the shift register.

A. TRUE
B. FALSE

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Question 57

Four bits shift register enables shift control signal in how many clock pulses?

A. Two clock pulses
B. Three clock pulses
C. Four clock pulses
D. Five clock pulses

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Question 58

How can parallel data be taken out of a shift register simultaneously?

A. Use the Q output of the first FF
B. Use the Q output of the last FF
C. Tie all of the Q outputs together
D. Use the Q output of each FF

View Answer

Question 59

In gated D latch, which of the following is the input symbol?

A. D
B. Q
C. EN
D. CLK

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Question 60

In PIPO shift register, parallel data can be taken out by ______

A. Using the Q output of the first flip-flop
B. Using the Q output of the last flip-flop
C. Using the Q output of the second flip-flop
D. Using the Q output of each flip-flop

View Answer

Question 61

In serial input serial output register, the data of ______ is accessed by the circuit.

A. Last flip-flop
B. First flip-flop
C. All flip-flops
D. No flip-flop

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Question 62

Shift registers are used to delay the data signal.

A. TRUE
B. FALSE

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Question 63

Shift registers comprise of which flip-flops?

A. D flip-flops
B. SR flip-flops
C. JK flip-flops
D. T flip-flops

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Question 64

The full form of SIPO is ___________

A. Serial-in Parallel-out
B. Parallel-in Serial-out
C. Serial-in Serial-out
D. Serial-In Peripheral-Out

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Question 65

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

A. 1110
B. 1
C. 101
D. 110

View Answer

Question 66

Time taken by the shift register to transfer the content is called _______

A. Clock duration
B. Bit duration
C. Word duration
D. Duration

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Question 67

Transfer of one bit of information at a time is called _______

A. Rotating
B. Serial transfer
C. Parallel transfer
D. Shifting

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Question 68

What is meant by the parallel load of a shift register?

A. All FFs are preset with data
B. Each FF is loaded with data, one at a time
C. Parallel shifting of data
D. All FFs are set with data

View Answer

Question 69

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms

View Answer