DAPZOI
Home Ask MCQ Quiz Topics Login


Shift Registers MCQ Questions & Answers

Shift Registers MCQs : This section focuses on the "Shift Registers". These Multiple Choice Questions (MCQs) should be practiced to improve the Shift Registers skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.




Question 1

What is meant by parallel load of a shift register?

A. All FFs are preset with data.
B. Each FF is loaded with data, one at a time.

View Answer

Question 2

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

A. 1110
B. 1
C. 101
D. 110

View Answer

Question 3

When is it important to use a three-state buffer?

A. when two or more outputs are connected to the same input
B. when all outputs are normally HIGH
C. when all outputs are normally LOW
D. when two or more outputs are connected to two or more inputs

View Answer

Question 4

In gated D latch, which of the following is the input symbol?

A. D
B. Q
C. EN
D. CLK

View Answer

Question 5

Time taken by the shift register to transfer the content is called _______

A. Clock duration
B. Bit duration
C. Word duration
D. Duration

View Answer

Question 6

Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.

A. 2
B. 3
C. 4
D. 5

View Answer

Question 7

Another way to connect devices to a shared data bus is to use a ________.

A. circulating gate
B. transceiver
C. bidirectional encoder
D. strobed latch

View Answer

Question 8

How can parallel data be taken out of a shift register simultaneously?

A. Use the Q output of the first FF.
B. Use the Q output of the last FF.
C. Tie all of the Q outputs together.
D. Use the Q output of each FF.

View Answer

Question 9

Clock divider slow down the input clock of the shift register.

A. TRUE
B. FALSE

View Answer

Question 10

In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A. 2
B. 6
C. 12
D. 24

View Answer

Question 11

Shift registers comprise of which flip-flops?

A. D flip-flops
B. SR flip-flops
C. JK flip-flops
D. T flip-flops

View Answer

Question 12

What is the function of a buffer circuit?

A. to provide an output that is inverted from that on the input
B. to provide an output that is equal to its input
C. to clean up the input
D. to clean up the output

View Answer

Question 13

What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

A. tristate
B. end around
C. universal
D. conversion

View Answer

Question 14

How is a strobe signal used when serially loading a shift register?

A. to turn the register on and off
B. to control the number of clocks
C. to determine which output Qs are used
D. to determine the FFs that will be used

View Answer

Question 15

How can parallel data be taken out of a shift register simultaneously?

A. Use the Q output of the first FF
B. Use the Q output of the last FF
C. Tie all of the Q outputs together
D. Use the Q output of each FF

View Answer

Question 16

What is meant by the parallel load of a shift register?

A. All FFs are preset with data
B. Each FF is loaded with data, one at a time
C. Parallel shifting of data
D. All FFs are set with data

View Answer

Question 17

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms

View Answer

Question 18

What does the output enable do on the 74395A chip?

A. It determines when data can be loaded.
B. It forces all outputs to go HIGH.
C. It forces all outputs to go LOW.
D. It activates the three-state buffer.

View Answer

Question 19

A 74HC195 4-bit parallel access shift register can be used for ________.

A. serial in/serial out operation
B. serial in/parallel out operation
C. parallel in/serial out operation
D. all of the above

View Answer

Question 20

Transfer of one bit of information at a time is called _______

A. Rotating
B. Serial transfer
C. Parallel transfer
D. Shifting

View Answer

Question 21

The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

A. 0
B. 10
C. 1000
D. 1111

View Answer

Question 22

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

A. 0
B. 1111
C. 111
D. 1000

View Answer

Question 23

Four bits shift register enables shift control signal in how many clock pulses?

A. Two clock pulses
B. Three clock pulses
C. Four clock pulses
D. Five clock pulses

View Answer

Question 24

By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.

A. parallel-in, serial, parallel
B. serial-in, parallel, serial
C. series-parallel-in, series, parallel
D. bidirectional in, parallel, series

View Answer

Question 25

If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

A. 11101011
B. 10111
C. 11110000
D. 0

View Answer

Question 26

Shift registers are used to delay the data signal.

A. TRUE
B. FALSE

View Answer

Question 27

If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

A. 1101000000
B. 11010000
C. 1100000000
D. 0

View Answer

Question 28

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.

A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms

View Answer

Question 29

To operate correctly, starting a ring shift counter requires:

A. clearing all the flip-flops
B. presetting one flip-flop and clearing all others
C. clearing one flip-flop and presetting all others
D. presetting all the flip-flops

View Answer

Question 30

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________

A. 16 us
B. 8 us
C. 4 us
D. 2 us

View Answer

Question 31

How would a latch circuit be used in a microprocessor system?

A. as transportation for Intel employees
B. for a group of data that is the same
C. as a set of common connections for transfer of data

View Answer

Question 32

What is the preset condition for a ring shift counter?

A. all FFs set to 1
B. all FFs cleared to 0
C. a single 0, the rest 1
D. a single 1, the rest 0

View Answer

Question 33

On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the fourth clock pulse, the sequence is ________.

A. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
B. Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
C. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

View Answer

Question 34

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

A. 1100
B. 11
C. 0
D. 1111

View Answer

Question 35

A modulus-12 ring counter requires a minimum of ________.

A. 10 flip-flops
B. 12 flip-flops
C. 6 flip-flops
D. 2 flip-flops

View Answer

Question 36

What is a transceiver circuit?

A. a buffer that transfers data from input to output
B. a buffer that transfers data from output to input
C. a buffer that can operate in both directions

View Answer

Question 37

How many clock pulses will be required to completely load serially a 5-bit shift register?

A. 2
B. 3
C. 4
D. 5

View Answer

Question 38

In serial input serial output register, the data of ______ is accessed by the circuit.

A. Last flip-flop
B. First flip-flop
C. All flip-flops
D. No flip-flop

View Answer

Question 39

The primary purpose of a three-state buffer is usually:

A. to provide isolation between the input device and the data bus
B. to provide the sink or source current required by any device connected to its output without loading down the output device
C. temporary data storage
D. to control data flow

View Answer

Question 40

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?

A. Tristate
B. End around
C. Universal
D. Conversion

View Answer

Question 41

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A. ring shift
B. clock
C. Johnson
D. binary

View Answer

Question 42

What is the difference between a ring shift counter and a Johnson shift counter?

A. There is no difference.
B. A ring is faster.
C. The feedback is reversed.
D. The Johnson is faster.

View Answer

Question 43

When the output of a tristate shift register is disabled, the output level is placed in a:

A. float state
B. LOW state
C. high-impedance state
D. float or high-impedance state

View Answer

Question 44

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.

A. 16 s
B. 8 s
C. 4 s
D. 2 s

View Answer

Question 45

On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock pulse, the sequence is ________.

A. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
B. Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
C. Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
D. Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1

View Answer

Question 46

To serially shift a nibble (four bits) of data into a shift register, there must be ________.

A. one clock pulse
B. four clock pulses
C. eight clock pulses
D. one clock pulse for each 1 in the data

View Answer

Question 47

In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

A. 1
B. 2
C. 4
D. 8

View Answer

Question 48

Ring shift and Johnson counters are:

A. synchronous counters
B. aynchronous counters
C. true binary counters
D. synchronous and true binary counters

View Answer

Question 49

Which is not characteristic of a shift register?

A. Serial in/parallel in
B. Serial in/parallel out
C. Parallel in/serial out
D. Parallel in/parallel out

View Answer

Question 50

Which type of device may be used to interface a parallel data format with external equipment's serial format?

A. key matrix
B. UART
C. memory chip
D. series in, parallel out

View Answer

Question 51

The full form of SIPO is ___________

A. Serial-in Parallel-out
B. Parallel-in Serial-out
C. Serial-in Serial-out
D. Serial-In Peripheral-Out

View Answer

Question 52

In PIPO shift register, parallel data can be taken out by ______

A. Using the Q output of the first flip-flop
B. Using the Q output of the last flip-flop
C. Using the Q output of the second flip-flop
D. Using the Q output of each flip-flop

View Answer

Question 53

The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.

A. 10111000
B. 10110111
C. 11110000
D. 11111100

View Answer

Question 54

What is the difference between a shift-right register and a shift-left register?

A. There is no difference.
B. the direction of the shift

View Answer

Question 55

With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.

A. 12 s
B. 120 s
C. 12 ms
D. 120 ms

View Answer

Question 56

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________

A. 0
B. 1111
C. 111
D. 1000

View Answer

Question 57

What is a recirculating register?

A. serial out connected to serial in
B. all Q outputs connected together
C. a register that can be used over again

View Answer

Question 58

In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.

A. 1110
B. 1
C. 1100
D. 1000

View Answer

Question 59

To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.

A. divide-by-4 clock pulse
B. sequence generator
C. strobe line
D. multiplexer

View Answer

Question 60

What are the three output conditions of a three-state buffer?

A. HIGH, LOW, float
B. 1, 0, float
C. both of the above
D. neither of the above

View Answer

Question 61

Computers operate on data internally in a ________ format.

A. tristate
B. universal
C. parallel
D. serial

View Answer

Question 62

Stepper motors have become popular in digital automation systems because ________.

A. of their low cost
B. they are driven by sequential digital signals
C. they can be used to provide repetitive mechanical movement
D. they are driven by sequential digital signals and can be used to provide repetitive mechanical movement

View Answer

Question 63

What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

A. parallel-in, parallel-out
B. parallel-in, serial-out
C. serial-in, parallel-out
D. serial-in, serial-out

View Answer

Question 64

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

A. 1.67 s
B. 26.67 s
C. 26.7 ms
D. 267 ms

View Answer

Question 65

The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

A. 10011100
B. 11000000
C. 1100
D. 11110000

View Answer

Question 66

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

A. 1100
B. 11
C. 0
D. 1111

View Answer

Question 67

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.

A. 1110
B. 1
C. 101
D. 110

View Answer

Question 68

A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

A. right, one
B. right, two
C. left, one
D. left, three

View Answer

Question 69

How much storage capacity does each stage in a shift register represent?

A. One bit
B. Two bits
C. Four bits (one nibble)
D. Eight bits (one byte)

View Answer