VLSI - Gate Logic MCQ Questions & Answers

VLSI - Gate Logic MCQs : This section focuses on the "VLSI - Gate Logic". These Multiple Choice Questions (MCQs) should be practiced to improve the VLSI - Gate Logic skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.

Question 1

As the number of inputs increases, the NAND gate delay

A. increases
B. decreases
C. does not vary
D. exponentially decreases

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Question 2

BiCMOS is used for ____ fan-out.

A. less
B. more
C. no
D. very less

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Question 3

Both NAND and NOR gates can be used in gate logic.

A. TRUE
B. FALSE

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Question 4

For a pseudo nMOS design the impedance of pull up and pull down ratio is

A. 04:01
B. 01:04
C. 03:01
D. 01:03

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Question 5

Gate logic is also called as

A. transistor logic
B. switch logic
C. complementary logic
D. restoring logic

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Question 6

In CMOS NAND gate, p transistors are connected in

A. series
B. parallel
C. cascade
D. random

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Question 7

NAND gate delay can be given as

A. Ʈint
B. Ʈint/n
C. n*Ʈint
D. 2n*Ʈint

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Question 8

The CMOS inverter has _____ power dissipation.

A. low
B. more
C. no
D. very less

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Question 9

Which can handle high capacitance load?

A. NAND
B. nMOS NAND
C. CMOS NAND
D. BiCMOS NAND

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Question 10

Which gate is faster?

A. AND
B. NAND
C. NOR
D. OR

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