Data Types MCQs : This section focuses on the "Data Types" in VHDL. These Multiple Choice Questions (MCQs) should be practiced to improve the VHDL skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
Which of the following is predefined data types in VHDL?
A. BIT
B. BOOLEAN
C. INTEGER
D. All of the above
Question 2
STD_LOGIC_VECTOR data types is built-in VHDL data types.
A. TRUE
B. FALSE
C. Can be true or false
D. Can not say
Question 3
The BIT data type can only have the value?
A. TRUE
B. FALSE
C. 0
D. null
Question 4
STD_LOGIC data type can have the value?
A. X
B. Z
C. 0
D. All of the above
Question 5
In STD_LOGIC, X stands for?
A. unknown
B. logic 0
C. logic 1
D. high impedance
Question 6
SIGNED and UNSIGNED data types are defined in which package?
A. std_logic_1164 package
B. std_logic package
C. std_logic_arith package
D. standard package
Question 7
What is the correct method to declare a SIGNED type signal 'x'?
A. SIGNAL x : IN SIGNED
B. SIGNAL x : IN SIGNED (7 DOWNTO 0)
C. SIGNAL x : IN SIGNED_VECTOR
D. SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0)
Question 8
A SUBTYPE can be defined as _________
A. A TYPE under a TYPE (nested)
B. A type of INTEGER datatype
C. A TYPE with some constraint
D. A TYPE without any constraint
Question 9
Which of the following is a SUBTYPE of INTEGER?
A. REAL
B. STD_LOGIC
C. CHARACTER
D. NATURAL
Question 10
When assigning a value to a STD_LOGIC_VECTOR type, the value must be enclosed in double quotes
A. TRUE
B. FALSE
C. Can be true or false
D. Can not say