Elements MCQs : This section focuses on the "Elements" in VHDL. These Multiple Choice Questions (MCQs) should be practiced to improve the VHDL skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
How many basic elements of VHDL?
A. 1
B. 2
C. 3
D. 4
View Answer
Ans : C
Explanation: There are the following three basic elements of VHDL : Entity, Architecture and Configuration.
Question 2
Which of the following is used to specify the input and output ports of the circuit?
A. Entity
B. Architecture
C. Configuration
D. All of the above
View Answer
Ans : A
Explanation: The Entity is used to specify the input and output ports of the circuit.
Question 3
Which of the following are the ports of Entity?
A. in
B. out
C. inout
D. All of the above
View Answer
Ans : D
Explanation: An Entity usually has one or more ports that can be inputs (in), outputs (out), input-outputs (inout), or buffer.
Question 4
Which of the following contain both concurrent and sequential statements?
A. Entity
B. Architecture
C. Configuration
D. None of the above
View Answer
Ans : B
Explanation: Architecture is the actual description of the design, which is used to describe how the circuit operates. It can contain both concurrent and sequential statements.
Question 5
configuration defines how the design hierarchy is linked together.
A. TRUE
B. FALSE
C. Can be true or false
D. Can not say
View Answer
Ans : A
Explanation: True, configuration defines how the design hierarchy is linked together.
Question 6
Which of the following is not defined by the entity?
A. Direction of any signal
B. Names of signal
C. Behavior of the signals
D. Different ports
View Answer
Ans : C
Explanation: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions
Question 7
Which of the following can be the name of an entity?
A. NAND
B. Nand_gate
C. Nand gate
D. AND
View Answer
Ans : B
Explanation: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option b is the only legal word
Question 8
What does the architecture of an entity define?
A. External interface
B. Ports of the entity
C. Internal functionality
D. Specifications
View Answer
Ans : C
Explanation: Basically, entity describes the interface to the VHDL model and its architecture describes the internal view of that entity. It describes the functionality and contains the statements which describe the behavior of entity.
Question 9
The statements in between the keyword BEGIN and END are called _______
A. Netlist
B. Declaration statement
C. Entity function
D. Concurrent statements
View Answer
Ans : D
Explanation: The proper word for the statements between BEGIN and END is Concurrent statements since they are executed concurrently. The code in between BEGIN and END describes the functionality or structure of the entity. BEGIN keyword specifies the starting of code.
Question 10
Port name consist of letters, digits, and underscores.
A. TRUE
B. FALSE
C. Can be true or false
D. Can not say
View Answer
Ans : A
Explanation: True, Port name consist of letters, digits, and underscores.