Types of VHDL Modelling MCQs : This section focuses on the "Types of VHDL Modelling" in VHDL. These Multiple Choice Questions (MCQs) should be practiced to improve the VHDL skills required for various interviews (campus interview, walk-in interview, company interview), placement, entrance exam and other competitive examinations.
Question 1
How many types of modeling styles in VHDL?
A. 1
B. 2
C. 3
D. 4
View Answer
Ans : C
Explanation: There are 3 types of modeling styles in VHDL : Data flow modeling, Behavioral modeling and Structural modeling.
Question 2
Data flow modeling also known as ?
A. Explains Behaviour
B. Design Equations
C. Connection of sub modules
D. All of the above
View Answer
Ans : B
Explanation: Data flow modeling is also known as Design Equations.
Question 3
Behavioral modeling contain?
A. Process statements
B. Sequential statements
C. Signal assignment statements
D. All of the above
View Answer
Ans : D
Explanation: Behavioral modeling may contain Process statements, Sequential statements, Signal assignment statements, and wait statements.
Question 4
Which of the following is used to specify the functionality and structure of the circuit?
A. Structural modeling
B. Behavioral modeling
C. Data flow modeling
D. None of the above
View Answer
Ans : A
Explanation: Structural modeling is used to specify the functionality and structure of the circuit.
Question 5
Data flow modeling works on Concurrent execution.
A. TRUE
B. FALSE
C. Can be true or false
D. Can not say
View Answer
Ans : A
Explanation: True, Data flow modeling works on Concurrent execution.
Question 6
What does modeling type refer to?
A. Type of ports in entity block of VHDL code
B. Type of description statements in architecture block of VHDL code
C. Type of data objects
D. Type of Signals
View Answer
Ans : B
Explanation: Modeling refers to the descriptive style we are using to describe our digital system. Modeling type is the type of statement used in architecture block to describe a specific system or circuit. It may define a structure or behavior or anything else
Question 7
In behavioral modeling, what do descriptive statements describe?
A. How the design is to be implemented
B. Netlist
C. How the system performs on given input values
D. Concurrent execution
View Answer
Ans : C
Explanation: Behavioral style specifies what a particular system does in a program. It gives the details of output values corresponding to the set of input values. In general, behavioral modeling use processes to describe the functioning of system, but no detail is provided regarding the design of the system
Question 8
Which of the following statement is used in structural modeling?
A. case
B. if-else
C. process()
D. portmap()
View Answer
Ans : D
Explanation: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap() function is used to map the specific component in the design.
Question 9
What is the basic unit of behavioral description?
A. Structure
B. Sequence
C. Process
D. Dataflow
View Answer
Ans : C
Explanation: The primary unit of a behavior description in VHDL is process which describes the behavior of system on various combinations of inputs. All the system is described by using processes and therefore, process is the basic unit.
Question 10
Structural modeling contain signal declarations, component instances, and port maps in component instance.
A. Yes
B. No
C. Can be yes or no
D. Can not say
View Answer
Ans : A
Explanation: Yes, Structural modeling contain signal declarations, component instances, and port maps in component instance.